Fujitsu MHC2040AT User Manuals

Table of Contents

• Front title

  1
• Preface

  6
• Important Alert Items

  10
• Contents

  12
• Illustrations

  17
• CHAPTER 1 Device Overview

  20
  • 1.1 Features

    21
    • 1.1.1 Functions and performance

      21
    • 1.1.2 Adaptability

      21
    • 1.1.3 Interface

      22
  • 1.2 Device Specifications

    23
    • 1.2.1 Specifications summary

      23
    • 1.2.2 Model and product number

      25
  • 1.3 Power Requirements

    25
  • 1.4 Environmental Specifications

    27
  • 1.5 Acoustic Noise

    27
  • 1.6 Shock and Vibration

    28
  • 1.7 Reliability

    28
  • 1.8 Error Rate

    29
  • 1.9 Media Defects

    29
• CHAPTER 2 Device Configuration

  30
  • 2.1 Device Configuration

    31
  • 2.2 System Configuration

    33
    • 2.2.1 ATA interface

      33
    • 2.2.2 1 drive connection

      33
    • 2.2.3 2 drives connection

      34
• CHAPTER 3 Installation Conditions

  36
  • 3.1 Dimensions

    37
  • 3.2 Mounting

    39
  • 3.3 Cable Connections

    43
    • 3.3.1 Device connector

      43
    • 3.3.2 Cable connector specifications

      44
    • 3.3.3 Device connection

      44
    • 3.3.4 Power supply connector (CN1)

      45
  • 3.4 Jumper Settings

    45
    • 3.4.1 Location of setting jumpers

      45
    • 3.4.2 Factory default setting

      46
    • 3.4.3 Master drive-slave drive setting

      46
    • 3.4.4 CSEL setting

      47
• CHAPTER 4 Theory of Device Operation

  50
  • 4.1 Outline

    51
  • 4.2 Subassemblies

    51
    • 4.2.1 Disk

      51
    • 4.2.2 Head

      51
    • 4.2.3 Spindle

      52
    • 4.2.4 Actuator

      52
    • 4.2.5 Air filter

      52
  • 4.3 Circuit Configuration

    53
  • 4.4 Power-on Sequence

    55
  • 4.5 Self-calibration

    56
    • 4.5.1 Self-calibration contents

      56
    • 4.5.2 Execution timing of self-calibration

      57
    • 4.5.3 Command processing during self-calibration

      58
  • 4.6 Read/write Circuit

    58
    • 4.6.1 Read/write preamplifier (PreAMP)

      58
    • 4.6.2 Write circuit

      59
    • 4.6.3 Read circuit

      61
    • 4.6.4 Digital PLL circuit

      62
  • 4.7 Servo Control

    63
    • 4.7.1 Servo control circuit

      63
    • 4.7.2 Data-surface servo format

      67
    • 4.7.3 Servo frame format

      67
    • 4.7.4 Actuator motor control

      68
    • 4.7.5 Spindle motor control

      69
• CHAPTER 5 Interface

  72
  • 5.1 Physical Interface

    73
    • 5.1.1 Interface signals

      73
    • 5.1.2 Signal assignment on the connector

      74
  • 5.2 Logical Interface

    77
    • 5.2.1 I/O registers

      78
    • 5.2.2 Command block registers

      79
    • 5.2.3 Control block registers

      84
  • 5.3 Host Commands

    84
    • 5.3.1 Command code and parameters

      85
    • 5.3.2 Command descriptions

      87
    • 5.3.3 Error posting

      139
  • 5.4 Command Protocol

    141
    • 5.4.1 Data transferring commands from device to host

      141
    • 5.4.2 Data transferring commands from host to device

      143
    • 5.4.3 Commands without data transfer

      145
    • 5.4.4 Other commands

      146
    • 5.4.5 DMA data transfer commands

      146
  • 5.5 Ultra DMA Feature Set

    148
    • 5.5.1 Overview

      148
    • 5.5.2 Phases of operation

      149
      • 5.5.2.1 Ultra DMA burst initiation phase

        149
      • 5.5.2.2 Data transfer phase

        150
      • 5.5.2.3 Ultra DMA burst termination phase

        150
    • 5.5.3 Ultra DMA data in commands

      151
      • 5.5.3.1 Initiating an Ultra DMA data in burst

        151
      • 5.5.3.2 The data in transfer

        152
      • 5.5.3.3 Pausing an Ultra DMA data in burst

        152
      • 5.5.3.4 Terminating an Ultra DMA data in burst

        153
    • 5.5.4 Ultra DMA data out commands

      156
      • 5.5.4.1 Initiating an Ultra DMA data out burst

        156
      • 5.5.4.2 The data out transfer

        156
      • 5.5.4.3 Pausing an Ultra DMA data out burst

        157
      • 5.5.4.4 Terminating an Ultra DMA data out burst

        158
    • 5.5.5 Ultra DMA CRC rules

      160
    • 5.5.6 Series termination required for Ultra DMA

      162
  • 5.6 Timing

    163
    • 5.6.1 PIO data transfer

      163
    • 5.6.2 Single word DMA data transfer

      165
    • 5.6.3 Multiword DMA data transfer

      166
    • 5.6.4 Transfer of Ultra DMA data

      167
      • 5.6.4.1 Starting of Ultra DMA data In Burst

        167
      • 5.6.4.2 Ultra DMA data burst timing requirements

        168
      • 5.6.4.3 Sustained Ultra DMA data in burst

        170
      • 5.6.4.4 Host pausing an Ultra DMA data in burst

        171
      • 5.6.4.5 Device terminating an Ultra DMA data in burst

        172
      • 5.6.4.6 Host terminating an Ultra DMA data in burst

        173
      • 5.6.4.7 Initiating an Ultra DMA data out burst

        174
      • 5.6.4.8 Sustained Ultra DMA data out burst

        175
      • 5.6.4.9 Device pausing an Ultra DMA data out burst

        176
      • 5.6.4.10 Host terminating an Ultra DMA data out burst

        177
      • 5.6.4.11 Device terminating an Ultra DMA data in burst

        178
    • 5.6.5 Power-on and reset

      179
• CHAPTER 6 Operations

  180
  • 6.1 Device Response to the Reset

    181
    • 6.1.1 Response to power-on

      181
    • 6.1.2 Response to hardware reset

      183
    • 6.1.3 Response to software reset

      184
    • 6.1.4 Response to diagnostic command

      185
  • 6.2 Address Translation

    186
    • 6.2.1 Default parameters

      186
    • 6.2.2 Logical address

      187
  • 6.3 Power Save

    188
    • 6.3.1 Power save mode

      188
    • 6.3.2 Power commands

      190
  • 6.4 Defect Management

    190
    • 6.4.1 Spare area

      191
    • 6.4.2 Alternating defective sectors

      191
  • 6.5 Read-Ahead Cache

    193
    • 6.5.1 Data buffer configuration

      193
    • 6.5.2 Caching operation

      193
    • 6.5.3 Usage of read segment

      195
      • 6.5.3.1 Mis-hit (no hit)

        195
      • 6.5.3.2 Sequential read

        196
      • 6.5.3.3 Full hit (hit all)

        199
      • 6.5.3.4 Partially hit

        200
  • 6.6 Write Cache

    201
• Glossary

  204
• Acronyms and Abbreviations

  208
• Index

  210
• Comment Form

  217
• spine

  218
• back

  218