User ManualTable of ContentsCover1Copy right2Revision History4Preface6Important Alert Items10Manual Organization12Contents14Illustrations19CHAPTER 1 Device Overview221.1 Features231.1.1 Functions and performance231.1.2 Adaptability231.1.3 Interface241.2 Device Specifications251.2.1 Specifications summary251.2.2 Model and product number261.3 Power Requirements261.4 Environmental Specifications281.5 Acoustic Noise291.6 Shock and Vibration291.7 Reliability301.8 Error Rate311.9 Media Defects31CHAPTER 2 Device Configuration322.1 Device Configuration332.2 System Configuration352.2.1 ATA interface352.2.2 1 drive connection352.2.3 2 drives connection35CHAPTER 3 Installation Conditions383.1 Dimensions393.2 Mounting413.3 Cable Connections473.3.1 Device connector473.3.2 Cable connector specifications483.3.3 Device connection483.3.4 Power supply connector (CN1)493.4 Jumper Settings493.4.1 Location of setting jumpers493.4.2 Factory default setting503.4.3 Master drive-slave drive setting503.4.4 CSEL setting51CHAPTER 4 Theory of Device Operation544.1 Outline554.2 Subassemblies554.2.1 Disk554.2.2 Head554.2.3 Spindle564.2.4 Actuator564.2.5 Air filter564.3 Circuit Configuration574.4 Power-on Sequence604.5 Self-calibration614.5.1 Self-calibration contents614.5.2 Execution timing of self-calibration624.5.3 Command processing during self-calibration634.6 Read/write Circuit634.6.1 Read/write preamplifier (HDIC)634.6.2 Write circuit644.6.3 Read circuit664.6.4 Digital PLL circuit674.7 Servo Control684.7.1 Servo control circuit684.7.2 Data-surface servo format714.7.3 Servo frame format734.7.4 Actuator motor control744.7.5 Spindle motor control75CHAPTER 5 Interface785.1 Physical Interface795.1.1 Interface signals795.1.2 Signal assignment on the connector805.2 Logical Interface835.2.1 I/O registers845.2.2 Command block registers855.2.3 Control block registers905.3 Host Commands905.3.1 Command code and parameters915.3.2 Command descriptions935.3.3 Error posting1605.4 Command Protocol1625.4.1 Data transferring commands from device to host1625.4.2 Data transferring commands from host to device1645.4.3 Commands without data transfer1665.4.4 Other commands1675.4.5 DMA data transfer commands1675.5 Ultra DMA Feature Set1695.5.1 Overview1695.5.2 Phases of operation1705.5.2.1 Ultra DMA burst initiation phase1705.5.2.2 Data transfer phase1715.5.2.3 Ultra DMA burst termination phase1715.5.3 Ultra DMA data in commands1725.5.3.1 Initiating an Ultra DMA data in burst1725.5.3.2 The data in transfer1735.5.3.3 Pausing an Ultra DMA data in burst1735.5.3.4 Terminating an Ultra DMA data in burst1745.5.4 Ultra DMA data out commands1775.5.4.1 Initiating an Ultra DMA data out burst1775.5.4.2 The data out transfer1775.5.4.3 Pausing an Ultra DMA data out burst1785.5.4.4 Terminating an Ultra DMA data out burst1795.5.5 Ultra DMA CRC rules1815.5.6 Series termination required for Ultra DMA Series termination resistors are required1835.6 Timing1845.6.1 PIO data transfer1845.6.2 Multiword DMA data transfer1865.6.3 Transfer of Ultra DMA data1875.6.3.1 Starting of Ultra DMA data In Burst1875.6.3.2 Ultra DMA data burst timing requirements1885.6.3.3 Sustained Ultra DMA data in burst1905.6.3.4 Host pausing an Ultra DMA data in burst1915.6.3.5 Device terminating an Ultra DMA data in burst1925.6.3.6 Host terminating an Ultra DMA data in burst1935.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings1945.6.3.8 Sustained Ultra DMA data out burst1955.6.3.9 Device pausing an Ultra DMA data out burst1965.6.3.10 Host terminating an Ultra DMA data out burst1975.6.3.11 Device terminating an Ultra DMA data in burst1985.6.4 Power-on and reset199CHAPTER 6 Operations2006.1 Device Response to the Reset2016.1.1 Response to power-on2016.1.2 Response to hardware reset2036.1.3 Response to software reset2046.1.4 Response to diagnostic command2056.2 Address Translation2066.2.1 Default parameters2066.2.2 Logical address2076.3 Power Save2086.3.1 Power save mode2086.3.2 Power commands2106.4 Defect Management2106.4.1 Spare area2116.4.2 Alternating defective sectors2116.5 Read-Ahead Cache2136.5.1 Data buffer configuration2136.5.2 Caching operation2136.5.3 Usage of read segment2156.5.3.1 Mis-hit (no hit)2156.5.3.2 Sequential read2166.5.3.3 Full hit (hit all)2196.5.3.4 Partially hit2206.6 Write Cache221Glossary224Acronyms and Abbreviations228Comment Form230Back231Size: 2.02 MBPages: 231Language: EnglishOpen manual