User ManualTable of ContentsChapter 1 About This Manual451.1 Processors Covered in this Manual451.2 Overview of The SYSTEM PROGRAMMING GUIDE471.3 Notational Conventions501.3.1 Bit and Byte Order501.3.2 Reserved Bits and Software Compatibility511.3.3 Instruction Operands521.3.4 Hexadecimal and Binary Numbers521.3.5 Segmented Addressing521.3.6 Syntax for CPUID, CR, and MSR Values531.3.7 Exceptions541.4 Related Literature55Chapter 2 System Architecture Overview572.1 Overview of the System-Level Architecture582.1.1 Global and Local Descriptor Tables612.1.1.1 Global and Local Descriptor Tables in IA-32e Mode612.1.2 System Segments, Segment Descriptors, and Gates612.1.2.1 Gates in IA-32e Mode622.1.3 Task-State Segments and Task Gates622.1.3.1 Task-State Segments in IA-32e Mode632.1.4 Interrupt and Exception Handling632.1.4.1 Interrupt and Exception Handling IA-32e Mode632.1.5 Memory Management642.1.5.1 Memory Management in IA-32e Mode642.1.6 System Registers652.1.6.1 System Registers in IA-32e Mode652.1.7 Other System Resources662.2 Modes of Operation662.3 System Flags and Fields in the EFLAGS Register682.3.1 System Flags and Fields in IA-32e Mode712.4 Memory-Management Registers712.4.1 Global Descriptor Table Register (GDTR)722.4.2 Local Descriptor Table Register (LDTR)722.4.3 IDTR Interrupt Descriptor Table Register732.4.4 Task Register (TR)732.5 Control Registers732.5.1 CPUID Qualification of Control Register Flags822.6 Extended Control Registers (including the XFEATURE_ENABLED_MASK Register)822.7 System Instruction Summary832.7.1 Loading and Storing System Registers852.7.2 Verifying of Access Privileges862.7.3 Loading and Storing Debug Registers872.7.4 Invalidating Caches and TLBs872.7.5 Controlling the Processor872.7.6 Reading Performance-Monitoring and Time-Stamp Counters882.7.6.1 Reading Counters in 64-Bit Mode892.7.7 Reading and Writing Model-Specific Registers892.7.7.1 Reading and Writing Model-Specific Registers in 64-Bit Mode902.7.8 Enabling Processor Extended States90Chapter 3 Protected-Mode Memory Management913.1 Memory Management Overview913.2 Using Segments933.2.1 Basic Flat Model933.2.2 Protected Flat Model943.2.3 Multi-Segment Model953.2.4 Segmentation in IA-32e Mode963.2.5 Paging and Segmentation973.3 Physical Address Space973.3.1 Intel® 64 Processors and Physical Address Space983.4 Logical and Linear Addresses983.4.1 Logical Address Translation in IA-32e Mode993.4.2 Segment Selectors993.4.3 Segment Registers1003.4.4 Segment Loading Instructions in IA-32e Mode1023.4.5 Segment Descriptors1033.4.5.1 Code- and Data-Segment Descriptor Types1063.5 System Descriptor Types1083.5.1 Segment Descriptor Tables1103.5.2 Segment Descriptor Tables in IA-32e Mode112Chapter 4 Paging1134.1 Paging Modes and Control Bits1134.1.1 Three Paging Modes1144.1.2 Paging-Mode Enabling1154.1.3 Paging-Mode Modifiers1174.1.4 Enumeration of Paging Features by CPUID1184.2 Hierarchical Paging Structures: an Overview1194.3 32-Bit Paging1204.4 PAE Paging1274.4.1 PDPTE Registers1284.4.2 Linear-Address Translation with PAE Paging1294.5 IA-32e Paging1354.6 Access Rights1444.7 Page-Fault Exceptions1464.8 Accessed and Dirty Flags1484.9 Paging and Memory Typing1494.9.1 Paging and Memory Typing When the PAT is Not Supported (Pentium Pro and Pentium II Processors)1494.9.2 Paging and Memory Typing When the PAT is Supported (Pentium III and More Recent Processor Families)1494.9.3 Caching Paging-Related Information about Memory Typing1504.10 Caching Translation Information1504.10.1 Translation Lookaside Buffers (TLBs)1514.10.1.1 Page Numbers, Page Frames, and Page Offsets1514.10.1.2 Caching Translations in TLBs1524.10.1.3 Details of TLB Use1524.10.1.4 Global Pages1534.10.2 Paging-Structure Caches1534.10.2.1 Caches for Paging Structures1534.10.2.2 Using the Paging-Structure Caches to Translate Linear Addresses1564.10.2.3 Multiple Cached Entries for a Single Paging-Structure Entry1574.10.3 Invalidation of TLBs and Paging-Structure Caches1584.10.3.1 Operations that Invalidate TLBs and Paging-Structure Caches1584.10.3.2 Recommended Invalidation1594.10.3.3 Optional Invalidation1604.10.4 Propagation of Paging-Structure Changes to Multiple Processors1614.11 Interactions with Virtual-Machine Extensions (VMX)1634.11.1 VMX Transitions1634.11.2 VMX Support for Address Translation1634.12 Using Paging for Virtual Memory1644.13 Mapping Segments to Pages164Chapter 5 Protection1675.1 Enabling and Disabling Segment and Page Protection1675.2 Fields and Flags Used for Segment-Level and Page-Level Protection1685.2.1 Code Segment Descriptor in 64-bit Mode1715.3 Limit Checking1725.3.1 Limit Checking in 64-bit Mode1735.4 Type Checking1735.4.1 Null Segment Selector Checking1755.4.1.1 NULL Segment Checking in 64-bit Mode1755.5 Privilege Levels1755.6 Privilege Level Checking When Accessing Data Segments1775.6.1 Accessing Data in Code Segments1795.7 Privilege Level Checking When Loading the SS Register1805.8 Privilege Level Checking When Transferring Program Control Between Code Segments1805.8.1 Direct Calls or Jumps to Code Segments1815.8.1.1 Accessing Nonconforming Code Segments1825.8.1.2 Accessing Conforming Code Segments1835.8.2 Gate Descriptors1845.8.3 Call Gates1855.8.3.1 IA-32e Mode Call Gates1865.8.4 Accessing a Code Segment Through a Call Gate1885.8.5 Stack Switching1915.8.5.1 Stack Switching in 64-bit Mode1945.8.6 Returning from a Called Procedure1945.8.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions1965.8.7.1 SYSENTER and SYSEXIT Instructions in IA-32e Mode1975.8.8 Fast System Calls in 64-bit Mode1985.9 Privileged Instructions1995.10 Pointer Validation2005.10.1 Checking Access Rights (LAR Instruction)2015.10.2 Checking Read/Write Rights (VERR and VERW Instructions)2025.10.3 Checking That the Pointer Offset Is Within Limits (LSL Instruction)2025.10.4 Checking Caller Access Privileges (ARPL Instruction)2035.10.5 Checking Alignment2055.11 Page-Level Protection2055.11.1 Page-Protection Flags2065.11.2 Restricting Addressable Domain2065.11.3 Page Type2065.11.4 Combining Protection of Both Levels of Page Tables2075.11.5 Overrides to Page Protection2075.12 Combining Page and Segment Protection2075.13 Page-Level Protection and Execute-Disable Bit2095.13.1 Detecting and Enabling the Execute-Disable Capability2095.13.2 Execute-Disable Page Protection2105.13.3 Reserved Bit Checking2115.13.4 Exception Handling213Chapter 6 Interrupt and Exception Handling2156.1 Interrupt and Exception Overview2156.2 Exception and Interrupt Vectors2166.3 Sources of Interrupts2166.3.1 External Interrupts2166.3.2 Maskable Hardware Interrupts2186.3.3 Software-Generated Interrupts2196.4 Sources of Exceptions2196.4.1 Program-Error Exceptions2196.4.2 Software-Generated Exceptions2206.4.3 Machine-Check Exceptions2206.5 Exception Classifications2206.6 Program or Task Restart2216.7 NonMaskable Interrupt (NMI)2226.7.1 Handling Multiple NMIs2236.8 Enabling and Disabling Interrupts2236.8.1 Masking Maskable Hardware Interrupts2236.8.2 Masking Instruction Breakpoints2246.8.3 Masking Exceptions and Interrupts When Switching Stacks2256.9 Priority Among Simultaneous Exceptions and Interrupts2256.10 Interrupt Descriptor Table (IDT)2266.11 IDT Descriptors2286.12 Exception and Interrupt Handling2296.12.1 Exception- or Interrupt-Handler Procedures2306.12.1.1 Protection of Exception- and Interrupt-Handler Procedures2326.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure2336.12.2 Interrupt Tasks2346.13 Error Code2356.14 Exception and Interrupt Handling in 64-bit Mode2366.14.1 64-Bit Mode IDT2376.14.2 64-Bit Mode Stack Frame2386.14.3 IRET in IA-32e Mode2396.14.4 Stack Switching in IA-32e Mode2396.14.5 Interrupt Stack Table2406.15 Exception and Interrupt Reference241Interrupt 0-Divide Error Exception (#DE)242Interrupt 1-Debug Exception (#DB)243Interrupt 2-NMI Interrupt244Interrupt 3-Breakpoint Exception (#BP)245Interrupt 4-Overflow Exception (#OF)246Interrupt 5-BOUND Range Exceeded Exception (#BR)247Interrupt 6-Invalid Opcode Exception (#UD)248Interrupt 7-Device Not Available Exception (#NM)250Interrupt 8-Double Fault Exception (#DF)252Interrupt 9-Coprocessor Segment Overrun255Interrupt 10-Invalid TSS Exception (#TS)256Interrupt 11-Segment Not Present (#NP)260Interrupt 12-Stack Fault Exception (#SS)262Interrupt 13-General Protection Exception (#GP)264Interrupt 14-Page-Fault Exception (#PF)268Interrupt 16-x87 FPU Floating-Point Error (#MF)272Interrupt 17-Alignment Check Exception (#AC)274Interrupt 18-Machine-Check Exception (#MC)276Interrupt 19-SIMD Floating-Point Exception (#XM)278Interrupts 32 to 255-User Defined Interrupts281Chapter 7 Task Management2837.1 Task Management Overview2837.1.1 Task Structure2837.1.2 Task State2847.1.3 Executing a Task2857.2 Task Management Data Structures2867.2.1 Task-State Segment (TSS)2867.2.2 TSS Descriptor2897.2.3 TSS Descriptor in 64-bit mode2907.2.4 Task Register2917.2.5 Task-Gate Descriptor2937.3 Task Switching2947.4 Task Linking2987.4.1 Use of Busy Flag To Prevent Recursive Task Switching3007.4.2 Modifying Task Linkages3007.5 Task Address Space3017.5.1 Mapping Tasks to the Linear and Physical Address Spaces3017.5.2 Task Logical Address Space3027.6 16-Bit Task-State Segment (TSS)3037.7 Task Management in 64-bit Mode304Chapter 8 Multiple-Processor Management3078.1 Locked Atomic Operations3088.1.1 Guaranteed Atomic Operations3098.1.2 Bus Locking3098.1.2.1 Automatic Locking3108.1.2.2 Software Controlled Bus Locking3118.1.3 Handling Self- and Cross-Modifying Code3128.1.4 Effects of a LOCK Operation on Internal Processor Caches3138.2 Memory Ordering3148.2.1 Memory Ordering in the Intel® Pentium® and Intel486™ Processors3148.2.2 Memory Ordering in P6 and More Recent Processor Families3158.2.3 Examples Illustrating the Memory-Ordering Principles3178.2.3.1 Assumptions, Terminology, and Notation3178.2.3.2 Neither Loads Nor Stores Are Reordered with Like Operations3188.2.3.3 Stores Are Not Reordered With Earlier Loads3198.2.3.4 Loads May Be Reordered with Earlier Stores to Different Locations3198.2.3.5 Intra-Processor Forwarding Is Allowed3208.2.3.6 Stores Are Transitively Visible3218.2.3.7 Stores Are Seen in a Consistent Order by Other Processors3218.2.3.8 Locked Instructions Have a Total Order3228.2.3.9 Loads and Stores Are Not Reordered with Locked Instructions3228.2.4 Out-of-Order Stores For String Operations3248.2.4.1 Memory-Ordering Model for String Operations on Write-back (WB) Memory3248.2.4.2 Examples Illustrating Memory-Ordering Principles for String Operations3258.2.5 Strengthening or Weakening the Memory-Ordering Model3288.3 Serializing Instructions3308.4 Multiple-Processor (MP) Initialization3328.4.1 BSP and AP Processors3338.4.2 MP Initialization Protocol Requirements and Restrictions3338.4.3 MP Initialization Protocol Algorithm for Intel Xeon Processors3348.4.4 MP Initialization Example3358.4.4.1 Typical BSP Initialization Sequence3368.4.4.2 Typical AP Initialization Sequence3388.4.5 Identifying Logical Processors in an MP System3398.5 Intel® Hyper-Threading Technology and Intel® Multi-Core Technology3418.6 Detecting Hardware Multi-Threading Support and Topology3418.6.1 Initializing Processors Supporting Hyper-Threading Technology3428.6.2 Initializing Multi-Core Processors3438.6.3 Executing Multiple Threads on an Intel® 64 or IA-32 Processor Supporting Hardware Multi-Threading3438.6.4 Handling Interrupts on an IA-32 Processor Supporting Hardware Multi-Threading3438.7 Intel® Hyper-Threading Technology Architecture3448.7.1 State of the Logical Processors3458.7.2 APIC Functionality3468.7.3 Memory Type Range Registers (MTRR)3468.7.4 Page Attribute Table (PAT)3478.7.5 Machine Check Architecture3478.7.6 Debug Registers and Extensions3478.7.7 Performance Monitoring Counters3488.7.8 IA32_MISC_ENABLE MSR3488.7.9 Memory Ordering3488.7.10 Serializing Instructions3488.7.11 MICROCODE UPDATE Resources3498.7.12 Self Modifying Code3498.7.13 Implementation-Specific Intel HT Technology Facilities3498.7.13.1 Processor Caches3498.7.13.2 Processor Translation Lookaside Buffers (TLBs)3508.7.13.3 Thermal Monitor3508.7.13.4 External Signal Compatibility3518.8 Multi-Core Architecture3528.8.1 Logical Processor Support3528.8.2 Memory Type Range Registers (MTRR)3528.8.3 Performance Monitoring Counters3538.8.4 IA32_MISC_ENABLE MSR3538.8.5 MICROCODE UPDATE Resources3538.9 Programming Considerations for Hardware Multi-Threading Capable Processors3538.9.1 Hierarchical Mapping of Shared Resources3548.9.2 Hierarchical Mapping of CPUID Extended Topology Leaf3568.9.3 Hierarchical ID of Logical Processors in an MP System3578.9.3.1 Hierarchical ID of Logical Processors with x2APIC ID3598.9.4 Algorithm for Three-Level Mappings of APIC_ID3608.9.5 Identifying Topological Relationships in a MP System3668.10 Management of Idle and Blocked Conditions3708.10.1 HLT Instruction3708.10.2 PAUSE Instruction3718.10.3 Detecting Support MONITOR/MWAIT Instruction3718.10.4 MONITOR/MWAIT Instruction3728.10.5 Monitor/Mwait Address Range Determination3738.10.6 Required Operating System Support3748.10.6.1 Use the PAUSE Instruction in Spin-Wait Loops3748.10.6.2 Potential Usage of MONITOR/MWAIT in C0 Idle Loops3758.10.6.3 Halt Idle Logical Processors3778.10.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops3778.10.6.5 Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources3788.10.6.6 Eliminate Execution-Based Timing Loops3788.10.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory379Chapter 9 Processor Management and Initialization3819.1 Initialization Overview3819.1.1 Processor State After Reset3829.1.2 Processor Built-In Self-Test (BIST)3829.1.3 Model and Stepping Information3859.1.4 First Instruction Executed3869.2 x87 FPU Initialization3869.2.1 Configuring the x87 FPU Environment3869.2.2 Setting the Processor for x87 FPU Software Emulation3879.3 Cache Enabling3889.4 Model-Specific Registers (MSRs)3899.5 Memory Type Range Registers (MTRRs)3899.6 Initializing SSE/SSE2/SSE3/SSSE3 Extensions3909.7 Software Initialization for Real-Address Mode Operation3909.7.1 Real-Address Mode IDT3919.7.2 NMI Interrupt Handling3919.8 Software Initialization for Protected-Mode Operation3919.8.1 Protected-Mode System Data Structures3929.8.2 Initializing Protected-Mode Exceptions and Interrupts3939.8.3 Initializing Paging3939.8.4 Initializing Multitasking3949.8.5 Initializing IA-32e Mode3949.8.5.1 IA-32e Mode System Data Structures3959.8.5.2 IA-32e Mode Interrupts and Exceptions3959.8.5.3 64-bit Mode and Compatibility Mode Operation3969.8.5.4 Switching Out of IA-32e Mode Operation3969.9 Mode Switching3979.9.1 Switching to Protected Mode3979.9.2 Switching Back to Real-Address Mode3989.10 Initialization and Mode Switching Example3999.10.1 Assembler Usage4029.10.2 STARTUP.ASM Listing4039.10.3 MAIN.ASM Source Code4139.10.4 Supporting Files4149.11 Microcode Update Facilities4169.11.1 Microcode Update4179.11.2 Optional Extended Signature Table4219.11.3 Processor Identification4219.11.4 Platform Identification4229.11.5 Microcode Update Checksum4249.11.6 Microcode Update Loader4259.11.6.1 Hard Resets in Update Loading4269.11.6.2 Update in a Multiprocessor System4269.11.6.3 Update in a System Supporting Intel Hyper-Threading Technology4269.11.6.4 Update in a System Supporting Dual-Core Technology4269.11.6.5 Update Loader Enhancements4279.11.7 Update Signature and Verification4279.11.7.1 Determining the Signature4289.11.7.2 Authenticating the Update4289.11.8 Pentium 4, Intel Xeon, and P6 Family Processor Microcode Update Specifications4299.11.8.1 Responsibilities of the BIOS4299.11.8.2 Responsibilities of the Calling Program4329.11.8.3 Microcode Update Functions4359.11.8.4 INT 15H-based Interface4359.11.8.5 Function 00H-Presence Test4369.11.8.6 Function 01H-Write Microcode Update Data4379.11.8.7 Function 02H-Microcode Update Control4429.11.8.8 Function 03H-Read Microcode Update Data4439.11.8.9 Return Codes444Chapter 10 Advanced Programmable Interrupt Controller (APIC)44710.1 Local and I/O APIC Overview44710.2 System Bus Vs. APIC Bus45110.3 the Intel® 82489DX External APIC, The APIC, the xAPIC, AND THE X2APIC45110.4 Local APIC45210.4.1 The Local APIC Block Diagram45210.4.2 Presence of the Local APIC45610.4.3 Enabling or Disabling the Local APIC45610.4.4 Local APIC Status and Location45710.4.5 Relocating the Local APIC Registers45810.4.6 Local APIC ID45810.4.7 Local APIC State45910.4.7.1 Local APIC State After Power-Up or Reset46010.4.7.2 Local APIC State After It Has Been Software Disabled46010.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)46110.4.7.4 Local APIC State After It Receives an INIT-Deassert IPI46110.4.8 Local APIC Version Register46110.5 Extended XAPIC (x2APIC)46210.5.1 DETECTING AND ENABLING x2APIC46210.5.1.1 Instructions to Access APIC Registers46310.5.1.2 APIC Register Address Space46410.5.1.3 Reserved Bit Checking46710.5.2 x2APIC Register Availability46810.5.3 MSR Access in x2APIC Mode46810.5.4 VM-exit Controls for MSRs and x2APIC Registers46810.5.5 Directed EOI with x2APIC Mode46910.5.6 x2APIC State Transitions47010.5.6.1 x2APIC States470x2APIC After RESET472x2APIC Transitions From x2APIC Mode473x2APIC Transitions From Disabled Mode473State Changes From xAPIC Mode to x2APIC Mode47310.5.7 System Software Transitions47310.5.8 CPUID Extensions And Topology Enumeration47410.5.8.1 Consistency of APIC IDs and CPUID47510.6 Handling Local Interrupts47610.6.1 Local Vector Table47610.6.2 Valid Interrupt Vectors47910.6.3 Error Handling48010.6.3.1 x2APIC Differences in Error Handling48110.6.4 APIC Timer48210.6.5 Local Interrupt Acceptance48410.7 Issuing Interprocessor Interrupts48410.7.1 Interrupt Command Register (ICR)48410.7.1.1 ICR Operation in x2APIC Mode49010.7.2 Determining IPI Destination49210.7.2.1 Physical Destination Mode49210.7.2.2 Logical Destination Mode49310.7.2.3 Logical Destination Mode in x2APIC Mode49510.7.2.4 Deriving Logical x2APIC ID from the Local x2APIC ID49610.7.2.5 Broadcast/Self Delivery Mode49710.7.2.6 Lowest Priority Delivery Mode49710.7.3 IPI Delivery and Acceptance49810.7.4 SELF IPI Register49810.8 System and APIC Bus Arbitration49910.9 Handling Interrupts50010.9.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors50010.9.2 Interrupt Handling with the P6 Family and Pentium Processors50110.9.3 Interrupt, Task, and Processor Priority50310.9.3.1 Task and Processor Priorities50410.9.4 Interrupt Acceptance for Fixed Interrupts50510.9.5 Signaling Interrupt Servicing Completion50710.9.5.1 Signaling Interrupt Servicing Completion in x2APIC Mode50710.9.6 Task Priority in IA-32e Mode50710.9.6.1 Interaction of Task Priorities between CR8 and APIC50810.10 Spurious Interrupt50910.11 APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors)51010.11.1 Bus Message Formats51110.12 Message Signalled Interrupts51110.12.1 Message Address Register Format51210.12.2 Message Data Register Format513Chapter 11 Memory Cache Control51511.1 Internal Caches, TLBs, and Buffers51511.2 Caching Terminology52111.3 Methods of Caching Available52211.3.1 Buffering of Write Combining Memory Locations52511.3.2 Choosing a Memory Type52611.3.3 Code Fetches in Uncacheable Memory52711.4 Cache Control Protocol52711.5 Cache Control52811.5.1 Cache Control Registers and Bits52911.5.2 Precedence of Cache Controls53411.5.2.1 Selecting Memory Types for Pentium Pro and Pentium II Processors53411.5.2.2 Selecting Memory Types for Pentium III and More Recent Processor Families53611.5.2.3 Writing Values Across Pages with Different Memory Types53711.5.3 Preventing Caching53811.5.4 Disabling and Enabling the L3 Cache53911.5.5 Cache Management Instructions53911.5.6 L1 Data Cache Context Mode54011.5.6.1 Adaptive Mode54011.5.6.2 Shared Mode54011.6 Self-Modifying Code54111.7 Implicit Caching (Pentium 4, Intel Xeon, and P6 Family Processors)54111.8 Explicit Caching54211.9 Invalidating the Translation Lookaside Buffers (TLBs)54311.10 Store Buffer54311.11 Memory Type Range Registers (MTRRs)54411.11.1 MTRR Feature Identification54611.11.2 Setting Memory Ranges with MTRRs54711.11.2.1 IA32_MTRR_DEF_TYPE MSR54711.11.2.2 Fixed Range MTRRs54811.11.2.3 Variable Range MTRRs54811.11.2.4 System-Management Range Register Interface55111.11.3 Example Base and Mask Calculations55211.11.3.1 Base and Mask Calculations for Greater-Than 36-bit Physical Address Support55411.11.4 Range Size and Alignment Requirement55511.11.4.1 MTRR Precedences55511.11.5 MTRR Initialization55511.11.6 Remapping Memory Types55611.11.7 MTRR Maintenance Programming Interface55611.11.7.1 MemTypeGet() Function55611.11.7.2 MemTypeSet() Function55811.11.8 MTRR Considerations in MP Systems56011.11.9 Large Page Size Considerations56111.12 Page Attribute Table (PAT)56211.12.1 Detecting Support for the PAT Feature56211.12.2 IA32_PAT MSR56311.12.3 Selecting a Memory Type from the PAT56411.12.4 Programming the PAT56411.12.5 PAT Compatibility with Earlier IA-32 Processors566Chapter 12 Intel® MMX™ Technology System Programming56712.1 Emulation of the MMX Instruction Set56712.2 The MMX State and MMX Register Aliasing56712.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag Word56912.3 Saving and Restoring the MMX State and Registers57012.4 Saving MMX State on Task or Context Switches57112.5 EXCEPTIONS That Can Occur When Executing MMX Instructions57112.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions57212.6 Debugging MMX Code572Chapter 13 System Programming For Instruction Set Extensions And Processor Extended States57513.1 Providing Operating System Support for SSE/SSE2/SSE3/SSSE3/SSE4 Extensions57513.1.1 Adding Support to an Operating System for SSE/SSE2/SSE3/SSSE3/SSE4 Extensions57613.1.2 Checking for SSE/SSE2/SSE3/SSSE3/SSE4 Extension Support57613.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions57713.1.4 Initialization of the SSE/SSE2/SSE3/SSSE3/SSE4 Extensions57713.1.5 Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE/SSE2/SSE3/SSSE3/SSE4 Instructions57913.1.6 Providing an Handler for the SIMD Floating-Point Exception (#XM)58113.1.6.1 Numeric Error flag and IGNNE#58213.2 Emulation of SSE/SSE2/SSE3/SSSE3/SSE4 Extensions58213.3 Saving and Restoring the SSE/SSE2/SSE3/SSSE3/SSE4 State58213.4 Saving the SSE/SSE2/SSE3/SSSE3/SSE4 State on Task or Context Switches58313.5 Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and SSE/SSE2/SSE3/SSSE3/SSE4 state on Task or Context Switches58313.5.1 Using the TS Flag to Control the Saving of the x87 FPU, MMX, SSE, SSE2, SSE3 SSSE3 and SSE4 State58413.6 XSAVE/XRSTOR and Processor Extended state management58613.6.1 XSAVE Header58713.7 Interoperability of XSAVE/XRSTOR and FXSAVE/FXRSTOR58913.8 Detection, Enumeration, Enabling Processor Extended State Support59113.8.1 Application Programming Model and Processor Extended States592Chapter 14 Power and Thermal Management59514.1 Enhanced Intel Speedstep® Technology59514.1.1 Software Interface For Initiating Performance State Transitions59514.2 P-State Hardware Coordination59614.3 System Software Considerations and Opportunistic processor Performance operation59814.3.1 Intel Dynamic Acceleration59814.3.2 System Software Interfaces for Opportunistic Processor Performance Operation59814.3.2.1 Discover Hardware Support and Enabling of Opportunistic Processor Operation59914.3.2.2 OS Control of Opportunistic Processor Performance Operation59914.3.2.3 Required Changes to OS Power Management P-state Policy60014.3.2.4 Application Awareness of Opportunistic Processor Operation (Optional)60114.3.3 Intel Turbo Boost Technology60214.3.4 Performance and Energy Bias Hint support60214.4 MWAIT Extensions for Advanced Power Management60314.5 Thermal Monitoring and Protection60414.5.1 Catastrophic Shutdown Detector60614.5.2 Thermal Monitor60614.5.2.1 Thermal Monitor 160614.5.2.2 Thermal Monitor 260614.5.2.3 Two Methods for Enabling TM260714.5.2.4 Performance State Transitions and Thermal Monitoring60814.5.2.5 Thermal Status Information60814.5.2.6 Adaptive Thermal Monitor61014.5.3 Software Controlled Clock Modulation61014.5.4 Detection of Thermal Monitor and Software Controlled Clock Modulation Facilities61214.5.5 On Die Digital Thermal Sensors61214.5.5.1 Digital Thermal Sensor Enumeration61214.5.5.2 Reading the Digital Sensor613Chapter 15 Machine-Check Architecture61715.1 Machine-Check Architecture61715.2 Compatibility with Pentium Processor61815.3 Machine-Check MSRs61815.3.1 Machine-Check Global Control MSRs61915.3.1.1 IA32_MCG_CAP MSR61915.3.1.2 IA32_MCG_STATUS MSR62115.3.1.3 IA32_MCG_CTL MSR62215.3.2 Error-Reporting Register Banks62215.3.2.1 IA32_MCi_CTL MSRs62215.3.2.2 IA32_MCi_STATUS MSRS62315.3.2.3 IA32_MCi_ADDR MSRs62715.3.2.4 IA32_MCi_MISC MSRs62815.3.2.5 IA32_MCi_CTL2 MSRs62915.3.2.6 IA32_MCG Extended Machine Check State MSRs63115.3.3 Mapping of the Pentium Processor Machine-Check Errors to the Machine-Check Architecture63315.4 Enhanced Cache Error reporting63415.5 Corrected Machine Check Error Interrupt63415.5.1 CMCI Local APIC Interface63515.5.2 System Software Recommendation for Managing CMCI and Machine Check Resources63715.5.2.1 CMCI Initialization63715.5.2.2 CMCI Threshold Management63815.5.2.3 CMCI Interrupt Handler63915.6 Recovery of Uncorrected Recoverable (UCR) Errors63915.6.1 Detection of Software Error Recovery Support64015.6.2 UCR Error Reporting and Logging64015.6.3 UCR Error Classification64115.6.4 UCR Error Overwrite Rules64315.7 Machine-Check Availability64415.8 Machine-Check Initialization64415.9 Interpreting the MCA Error Codes64515.9.1 Simple Error Codes64615.9.2 Compound Error Codes64715.9.2.1 Correction Report Filtering (F) Bit64715.9.2.2 Transaction Type (TT) Sub-Field64815.9.2.3 Level (LL) Sub-Field64815.9.2.4 Request (RRRR) Sub-Field64815.9.2.5 Bus and Interconnect Errors64915.9.2.6 Memory Controller Errors65015.9.3 Architecturally Defined UCR Errors65015.9.3.1 Architecturally Defined SRAO Errors65015.9.3.2 Architecturally Defined SRAR Errors65215.9.4 Multiple MCA Errors65415.9.5 Machine-Check Error Codes Interpretation65515.10 Guidelines for Writing Machine-Check Software65515.10.1 Machine-Check Exception Handler65615.10.2 Pentium Processor Machine-Check Exception Handling65715.10.3 Logging Correctable Machine-Check Errors65815.10.4 Machine-Check Software Handler Guidelines for Error Recovery66015.10.4.1 Machine-Check Exception Handler for Error Recovery66015.10.4.2 Corrected Machine-Check Handler for Error Recovery666Chapter 16 Debugging, Profiling Branches and Time- Stamp Counter66916.1 Overview of Debug Support Facilities66916.2 Debug Registers67016.2.1 Debug Address Registers (DR0-DR3)67216.2.2 Debug Registers DR4 and DR567216.2.3 Debug Status Register (DR6)67216.2.4 Debug Control Register (DR7)67316.2.5 Breakpoint Field Recognition67416.2.6 Debug Registers and Intel® 64 Processors67616.3 Debug Exceptions67716.3.1 Debug Exception (#DB)-Interrupt Vector 167716.3.1.1 Instruction-Breakpoint Exception Condition67816.3.1.2 Data Memory and I/O Breakpoint Exception Conditions68016.3.1.3 General-Detect Exception Condition68016.3.1.4 Single-Step Exception Condition68016.3.1.5 Task-Switch Exception Condition68116.3.2 Breakpoint Exception (#BP)-Interrupt Vector 368116.4 Last Branch, Interrupt, and Exception Recording Overview68216.4.1 IA32_DEBUGCTL MSR68216.4.2 Monitoring Branches, Exceptions, and Interrupts68416.4.3 Single-Stepping on Branches, Exceptions, and Interrupts68416.4.4 Branch Trace Messages68516.4.5 Branch Trace Store (BTS)68516.4.6 CPL-Qualified Branch Trace Mechanism68616.4.7 Freezing LBR and Performance Counters on PMI68616.4.8 LBR Stack68716.4.8.1 LBR Stack and Intel® 64 Processors68816.4.8.2 LBR Stack and IA-32 Processors68816.4.8.3 Last Exception Records and Intel 64 Architecture68916.4.9 BTS and DS Save Area68916.4.9.1 DS Save Area and IA-32e Mode Operation69316.4.9.2 Setting Up the DS Save Area69616.4.9.3 Setting Up the BTS Buffer69716.4.9.4 Setting Up CPL-Qualified BTS69816.4.9.5 Writing the DS Interrupt Service Routine69916.5 Last Branch, Interrupt, and Exception Recording (Intel® Core™2 Duo and Intel® Atom™ Processor Family)70016.5.1 LBR Stack70116.6 Last Branch, Interrupt, and Exception Recording (Intel® Core™i7 Processor Family)70116.6.1 LBR Stack70216.6.2 Filtering of Last Branch Records70316.7 Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture)70416.7.1 MSR_DEBUGCTLA MSR70516.7.2 LBR Stack for Processors Based on Intel NetBurst Microarchitecture70616.7.3 Last Exception Records70816.8 Last Branch, Interrupt, and Exception Recording (Intel® Core™ Solo and Intel® Core™ Duo Processors)70916.9 Last Branch, Interrupt, and Exception Recording (Pentium M Processors)71116.10 Last Branch, Interrupt, and Exception Recording (P6 Family Processors)71316.10.1 DEBUGCTLMSR Register71316.10.2 Last Branch and Last Exception MSRs71416.10.3 Monitoring Branches, Exceptions, and Interrupts71516.11 Time-Stamp Counter71616.11.1 Invariant TSC71716.11.2 IA32_TSC_AUX Register and RDTSCP Support718Chapter 17 8086 Emulation71917.1 Real-Address Mode71917.1.1 Address Translation in Real-Address Mode72117.1.2 Registers Supported in Real-Address Mode72217.1.3 Instructions Supported in Real-Address Mode72217.1.4 Interrupt and Exception Handling72417.2 Virtual-8086 Mode72617.2.1 Enabling Virtual-8086 Mode72717.2.2 Structure of a Virtual-8086 Task72717.2.3 Paging of Virtual-8086 Tasks72817.2.4 Protection within a Virtual-8086 Task72917.2.5 Entering Virtual-8086 Mode72917.2.6 Leaving Virtual-8086 Mode73217.2.7 Sensitive Instructions73317.2.8 Virtual-8086 Mode I/O73317.2.8.1 I/O-Port-Mapped I/O73317.2.8.2 Memory-Mapped I/O73417.2.8.3 Special I/O Buffers73417.3 Interrupt and Exception Handling in Virtual-8086 Mode73417.3.1 Class 1-Hardware Interrupt and Exception Handling in Virtual-8086 Mode73617.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate73617.3.1.2 Handling an Interrupt or Exception With an 8086 Program Interrupt or Exception Handler73817.3.1.3 Handling an Interrupt or Exception Through a Task Gate73917.3.2 Class 2-Maskable Hardware Interrupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism74017.3.3 Class 3-Software Interrupt Handling in Virtual-8086 Mode74217.3.3.1 Method 1: Software Interrupt Handling74517.3.3.2 Methods 2 and 3: Software Interrupt Handling74617.3.3.3 Method 4: Software Interrupt Handling74617.3.3.4 Method 5: Software Interrupt Handling74617.3.3.5 Method 6: Software Interrupt Handling74717.4 Protected-Mode Virtual Interrupts748Chapter 18 Mixing 16-Bit and 32-Bit Code75118.1 Defining 16-Bit and 32-Bit Program Modules75218.2 Mixing 16-Bit and 32-Bit Operations Within a Code Segment75218.3 Sharing Data Among Mixed-Size Code Segments75418.4 Transferring Control Among Mixed-Size Code Segments75418.4.1 Code-Segment Pointer Size75518.4.2 Stack Management for Control Transfer75518.4.2.1 Controlling the Operand-Size Attribute For a Call75718.4.2.2 Passing Parameters With a Gate75818.4.3 Interrupt Control Transfers75818.4.4 Parameter Translation75818.4.5 Writing Interface Procedures759Chapter 19 Architecture Compatibility76119.1 Processor Families and Categories76119.2 Reserved Bits76219.3 Enabling New Functions and Modes76219.4 Detecting the Presence of New Features Through Software76319.5 Intel MMX Technology76319.6 Streaming SIMD Extensions (SSE)76319.7 Streaming SIMD Extensions 2 (SSE2)76419.8 Streaming SIMD Extensions 3 (SSE3)76419.9 Additional Streaming SIMD Extensions76419.10 Intel Hyper-Threading Technology76519.11 Multi-Core Technology76519.12 Specific Features of Dual-Core Processor76519.13 New Instructions In the Pentium and Later IA-32 Processors76519.13.1 Instructions Added Prior to the Pentium Processor76619.14 Obsolete Instructions76719.15 Undefined Opcodes76719.16 New Flags in the EFLAGS Register76719.16.1 Using EFLAGS Flags to Distinguish Between 32-Bit IA-32 Processors76819.17 Stack Operations76819.17.1 PUSH SP76819.17.2 EFLAGS Pushed on the Stack76919.18 x87 FPU76919.18.1 Control Register CR0 Flags76919.18.2 x87 FPU Status Word77019.18.2.1 Condition Code Flags (C0 through C3)77019.18.2.2 Stack Fault Flag77119.18.3 x87 FPU Control Word77119.18.4 x87 FPU Tag Word77119.18.5 Data Types77219.18.5.1 NaNs77219.18.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal Formats77219.18.6 Floating-Point Exceptions77319.18.6.1 Denormal Operand Exception (#D)77319.18.6.2 Numeric Overflow Exception (#O)77319.18.6.3 Numeric Underflow Exception (#U)77419.18.6.4 Exception Precedence77419.18.6.5 CS and EIP For FPU Exceptions77419.18.6.6 FPU Error Signals77419.18.6.7 Assertion of the FERR# Pin77519.18.6.8 Invalid Operation Exception On Denormals77519.18.6.9 Alignment Check Exceptions (#AC)77619.18.6.10 Segment Not Present Exception During FLDENV77619.18.6.11 Device Not Available Exception (#NM)77619.18.6.12 Coprocessor Segment Overrun Exception77619.18.6.13 General Protection Exception (#GP)77619.18.6.14 Floating-Point Error Exception (#MF)77619.18.7 Changes to Floating-Point Instructions77719.18.7.1 FDIV, FPREM, and FSQRT Instructions77719.18.7.2 FSCALE Instruction77719.18.7.3 FPREM1 Instruction77719.18.7.4 FPREM Instruction77719.18.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions77719.18.7.6 FPTAN Instruction77819.18.7.7 Stack Overflow77819.18.7.8 FSIN, FCOS, and FSINCOS Instructions77819.18.7.9 FPATAN Instruction77819.18.7.10 F2XM1 Instruction77819.18.7.11 FLD Instruction77819.18.7.12 FXTRACT Instruction77919.18.7.13 Load Constant Instructions77919.18.7.14 FSETPM Instruction77919.18.7.15 FXAM Instruction78019.18.7.16 FSAVE and FSTENV Instructions78019.18.8 Transcendental Instructions78019.18.9 Obsolete Instructions78019.18.10 WAIT/FWAIT Prefix Differences78119.18.11 Operands Split Across Segments and/or Pages78119.18.12 FPU Instruction Synchronization78119.19 Serializing Instructions78119.20 FPU and Math Coprocessor Initialization78219.20.1 Intel® 387 and Intel® 287 Math Coprocessor Initialization78219.20.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor Initialization78219.21 Control Registers78419.22 Memory Management Facilities78519.22.1 New Memory Management Control Flags78519.22.1.1 Physical Memory Addressing Extension78519.22.1.2 Global Pages78619.22.1.3 Larger Page Sizes78619.22.2 CD and NW Cache Control Flags78619.22.3 Descriptor Types and Contents78619.22.4 Changes in Segment Descriptor Loads78719.23 Debug Facilities78719.23.1 Differences in Debug Register DR678719.23.2 Differences in Debug Register DR778719.23.3 Debug Registers DR4 and DR578719.24 Recognition of Breakpoints78819.25 Exceptions and/or Exception Conditions78819.25.1 Machine-Check Architecture79019.25.2 Priority OF Exceptions79019.26 Interrupts79019.26.1 Interrupt Propagation Delay79019.26.2 NMI Interrupts79019.26.3 IDT Limit79119.27 Advanced Programmable Interrupt Controller (APIC)79119.27.1 Software Visible Differences Between the Local APIC and the 82489DX79119.27.2 New Features Incorporated in the Local APIC for the P6 Family and Pentium Processors79219.27.3 New Features Incorporated in the Local APIC of the Pentium 4 and Intel Xeon Processors79219.28 Task Switching and TSs79219.28.1 P6 Family and Pentium Processor TSS79319.28.2 TSS Selector Writes79319.28.3 Order of Reads/Writes to the TSS79319.28.4 Using A 16-Bit TSS with 32-Bit Constructs79319.28.5 Differences in I/O Map Base Addresses79319.29 Cache Management79419.29.1 Self-Modifying Code with Cache Enabled79519.29.2 Disabling the L3 Cache79619.30 Paging79619.30.1 Large Pages79619.30.2 PCD and PWT Flags79619.30.3 Enabling and Disabling Paging79719.31 Stack Operations79719.31.1 Selector Pushes and Pops79719.31.2 Error Code Pushes79819.31.3 Fault Handling Effects on the Stack79819.31.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate79819.32 Mixing 16- and 32-Bit Segments79919.33 Segment and Address Wraparound79919.33.1 Segment Wraparound80019.34 Store Buffers and Memory Ordering80019.35 Bus Locking80219.36 Bus Hold80219.37 Model-Specific Extensions to the IA-3280219.37.1 Model-Specific Registers80319.37.2 RDMSR and WRMSR Instructions80319.37.3 Memory Type Range Registers80319.37.4 Machine-Check Exception and Architecture80419.37.5 Performance-Monitoring Counters80419.38 Two Ways to Run Intel 286 Processor Tasks805Size: 5.71 MBPages: 806Language: EnglishOpen manual
