Intel i5-4200H User Manuals

Table of Contents

• Contents

  3
  • Figures

    6
  • Tables

    7
• Revision History

  9
• 1.0 Introduction

  10
  • 1.1 Supported Technologies

    11
  • 1.2 Interfaces

    12
  • 1.3 Power Management Support

    12
  • 1.4 Thermal Management Support

    13
  • 1.5 Package Support

    13
  • 1.6 Processor Testability

    13
  • 1.7 Terminology

    13
  • 1.8 Related Documents

    17
• 2.0 Interfaces

  18
  • 2.1 System Memory Interface

    18
    • 2.1.1  System Memory Technology Supported

      18
    • 2.1.2 System Memory Timing Support

      19
    • 2.1.3 System Memory Organization Modes

      20
    • 2.1.4 System Memory Frequency

      21
    • 2.1.5  Intel® Fast Memory Access (Intel® FMA) Technology Enhancements

      21
    • 2.1.6  Data Scrambling

      22
    • 2.1.7 DRAM Clock Generation

      22
    • 2.1.8 DRAM Reference Voltage Generation

      22
  • 2.2 PCI Express* Interface

    23
    • 2.2.1 PCI Express* Support

      23
    • 2.2.2 PCI Express* Architecture

      24
    • 2.2.3 PCI Express* Configuration Mechanism

      24
  • 2.3 Direct Media Interface (DMI)

    26
  • 2.4 Processor Graphics

    28
  • 2.5 Processor Graphics Controller (GT)

    28
    • 2.5.1 3D and Video Engines for Graphics Processing

      29
    • 2.5.2 Multi Graphics Controllers Multi-Monitor Support

      31
  • 2.6 Digital Display Interface (DDI)

    31
  • 2.7 Intel® Flexible Display Interface (Intel® FDI)

    37
  • 2.8 Platform Environmental Control Interface (PECI)

    38
    • 2.8.1 PECI Bus Architecture

      38
• 3.0 Technologies

  40
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    40
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    44
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    45
  • 3.4 Intel® Turbo Boost Technology 2.0

    46
  • 3.5 Intel® Advanced Vector Extensions 2.0 (Intel® AVX2)

    47
  • 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    47
  • 3.7  Intel® Transactional Synchronization Extensions - New Instructions (Intel® TSX-NI)

    48
  • 3.8 Intel® 64 Architecture x2APIC

    48
  • 3.9  Power Aware Interrupt Routing (PAIR)

    49
  • 3.10 Execute Disable Bit

    49
  • 3.11  Supervisor Mode Execution Protection (SMEP)

    50
• 4.0 Power Management

  51
  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    52
  • 4.2 Processor Core Power Management

    53
    • 4.2.1 Enhanced Intel® SpeedStep® Technology Key Features

      53
    • 4.2.2 Low-Power Idle States

      54
    • 4.2.3 Requesting Low-Power Idle States

      55
    • Core C-State Rules

      56
    • Package C-States

      57
    • 4.2.6 Package C-States and Display Resolutions

      61
  • 4.3 Integrated Memory Controller (IMC) Power Management

    63
    • 4.3.1 Disabling Unused System Memory Outputs

      63
    • 4.3.2 DRAM Power Management and Initialization

      63
      • 4.3.2.1 Initialization Role of CKE

        65
      • 4.3.2.2 Conditional Self-Refresh

        65
      • 4.3.2.3 Dynamic Power-Down

        65
      • 4.3.2.4 DRAM I/O Power Management

        66
    • 4.3.3  DRAM Running Average Power Limitation (RAPL)

      66
    • 4.3.4 DDR Electrical Power Gating (EPG)

      66
  • 4.4 PCI Express* Power Management

    66
  • 4.5 Direct Media Interface (DMI) Power Management

    66
  • 4.6 Graphics Power Management

    66
    • 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM)

      66
    • 4.6.2 Graphics Render C-State

      67
    • 4.6.3 Intel® Smart 2D Display Technology (Intel® S2DDT)

      67
    • 4.6.4 Intel® Graphics Dynamic Frequency

      67
    • 4.6.5  Intel® Display Power Saving Technology (Intel® DPST)

      67
    • 4.6.6 Intel® Automatic Display Brightness

      68
    • 4.6.7 Intel® Seamless Display Refresh Rate Technology (Intel® SDRRS Technology)

      68
• 5.0 Thermal Management

  69
  • 5.1 Thermal Considerations

    69
  • 5.2 Intel® Turbo Boost Technology 2.0 Power Monitoring

    70
  • 5.3 Intel® Turbo Boost Technology 2.0 Power Control

    70
    • 5.3.1 Package Power Control

      70
    • 5.3.2 Turbo Time Parameter

      71
  • 5.4 Configurable TDP (cTDP) and Low-Power Mode

    71
    • 5.4.1 Configurable TDP

      71
    • 5.4.2 Low-Power Mode

      72
  • 5.5 Thermal and Power Specifications

    72
  • 5.6 Thermal Management Features

    76
    • 5.6.1 Adaptive Thermal Monitor

      76
      • 5.6.1.1 Thermal Control Circuit (TCC) Activation Offset

        77
      • 5.6.1.2 Frequency / Voltage Control

        77
      • 5.6.1.3 Clock Modulation

        78
    • 5.6.2 Digital Thermal Sensor

      78
      • 5.6.2.1 Digital Thermal Sensor Accuracy (Taccuracy)

        79
      • 5.6.2.2  Fan Speed Control with Digital Thermal Sensor

        79
    • 5.6.3 PROCHOT# Signal

      79
      • 5.6.3.1 Bi-Directional PROCHOT#

        79
      • 5.6.3.2 Voltage Regulator Protection using PROCHOT#

        80
      • 5.6.3.3 Thermal Solution Design and PROCHOT# Behavior

        80
      • 5.6.3.4 Low-Power States and PROCHOT# Behavior

        80
      • 5.6.3.5 THERMTRIP# Signal

        80
      • 5.6.3.6 Critical Temperature Detection

        80
    • 5.6.4 On-Demand Mode

      81
      • 5.6.4.1 MSR Based On-Demand Mode

        81
      • 5.6.4.2 I/O Emulation-Based On-Demand Mode

        81
    • 5.6.5 Intel® Memory Thermal Management

      81
• 6.0 Signal Description

  83
  • 6.1 System Memory Interface Signals

    84
  • 6.2 Memory Reference Compensation Signals

    86
  • 6.3 Reset and Miscellaneous Signals

    86
  • 6.4 PCI Express* Interface Signals

    87
  • 6.5 embedded DisplayPort* (eDP*) Signals

    87
  • 6.6 Display Interface Signals

    88
  • 6.7 Direct Media Interface (DMI)

    88
  • 6.8 Phase Locked Loop (PLL) Signals

    88
  • 6.9 Testability Signals

    89
  • 6.10 Error and Thermal Protection Signals

    90
  • 6.11 Power Sequencing Signals

    90
  • 6.12 Processor Power Signals

    91
  • 6.13 Sense Signals

    91
  • 6.14 Ground and Non-Critical to Function (NCTF) Signals

    91
  • 6.15 Processor Internal Pull-Up / Pull-Down Terminations

    92
• 7.0 Electrical Specifications

  93
  • 7.1 Integrated Voltage Regulator

    93
  • 7.2 Power and Ground Pins

    93
  • 7.3 VCC Voltage Identification (VID)

    93
  • 7.4 Reserved or Unused Signals

    98
  • 7.5 Signal Groups

    98
  • 7.6 Test Access Port (TAP) Connection

    100
  • 7.7  DC Specifications

    100
  • 7.8 Voltage and Current Specifications

    101
    • 7.8.1 Platform Environment Control Interface (PECI) DC Characteristics

      106
    • 7.8.2 Input Device Hysteresis

      107
• 8.0 Package Specifications

  108
  • 8.1 Package Mechanical Specifications

    108
    • 8.1.1 Processor Mass

      110
  • 8.2 Package Loading Specifications

    110
  • 8.3 Package Storage Specifications

    111
• 9.0 Processor Pin and Signal Information

  112
• 10.0 DDR Data Swizzling

  135