Omega Engineering OMG-ULTRACOMM422 RS-422/485 User Manuals

Table of Contents

• INTRODUCTION

  1
• OVERVIEW

  1
• W HAT ’S INCLUDED

  1
• FACTORY DEFAULT SETTINGS

  1
• CARD SETUP

  2
• A DDRESS SELECTION

  2
• JUMPER SELECTIONS

  4
• IRQ Selection

  4
• INTERRUPT M ODES

  5
• RS-485 ENABLE M ODES

  6
• Interface Mode Examples J1D – J4D

  7
• Interface Mode Examples J1D – J4D (continued)

  8
• LINE TERMINATION

  9
• CLOCK M ODES

  10
• BAUD RATES AND DIVISORS FOR THE ‘DIV1’ MODE

  11
• BAUD RATES AND DIVISORS FOR THE ‘DIV2’ MODE

  12
• INSTALLATION

  13
• OPERATING SYSTEM INSTALLATION

  13
• For Windows Users

  13
• Other Operating Systems

  13
• TECHNICAL DESCRIPTION

  14
• FEATURES

  14
• INTERRUPTS

  15
• W HY USE AN ISP?

  16
• CONNECTOR PIN A SSIGNMENTS

  17
• DB-9 Pin Assignments

  17
• DB-37 Connector Pin Assignments

  17
• SPECIFICATIONS

  18
• ENVIRONMENTAL SPECIFICATIONS

  18
• M ANUFACTURING

  18
• POWER CONSUMPTION

  18
• M EAN TIME BETWEEN FAILURES (MTBF)

  18
• PHYSICAL DIMENSIONS

  18
• APPENDIX A - TROUBLESHOOTING

  19
• APPENDIX C - ELECTRICAL INTERFACE

  22
• RS-422

  22
• RS-485

  22
• APPENDIX D - ASYNCHRONOUS COMMUNICATIONS

  23
• APPENDIX E - SILK-SCREEN

  24
• APPENDIX F - COMPLIANCE NOTICES

  25
• FEDERAL COMMUNICATIONS COMMISSION STATEMENT

  25
• EMC DIRECTIVE STATEMENT

  25
• Figure 1 - Available Address Combinations

  2
• Figure 2 - Address Selection Table

  3
• Figure 3 - Port to Connector Table

  3
• Figure 4 - Header J1A, Normal IRQ Mode

  5
• Figure 5 - Header J1A & J2A, Shared IRQ Mode

  5
• Figure 6- Headers J1D- J4D, RS-422

  7
• Figure 7 - Headers J1D- J4D, RS-485 ‘Auto’ Enabled, with ‘No Echo’

  7
• Figure 8 - Headers J1D- J4D, RS-485 ‘Auto’ Enabled, with ‘Echo’

  7
• Figure 9 - Headers J1D- J4D, RS-485 ‘RTS’ Enabled, with ‘No Echo’

  8
• Figure 10 - Headers J1D- J4D, RS-485 ‘RTS’ Enabled, with ‘Echo’

  8
• Figure 11 - Headers J1E - J4E, Line Termination

  9
• Figure 12 - Clocking Mode 'Divide By 4’

  10
• Figure 13 - Clocking Mode 'Divide By 2’

  10
• Figure 14 - Clocking Mode 'Divide By 1’

  10
• Figure 15 - Asynchronous Communications Bit Diagram

  23