User ManualTable of ContentsTable of Contents3List of Figures12List of Tables14Chapter 1 Preface161.1 General Terms161.2 Buffer Types18Table 1.1 Buffer Types181.3 Register Nomenclature19Table 1.2 Register Bit Types19Chapter 2 Introduction202.1 General Description202.2 Block Diagram21Figure 2.1 Internal LAN9312 Block Diagram212.2.1 System Clocks/Reset/PME Controller222.2.2 System Interrupt Controller222.2.3 Switch Fabric232.2.4 Ethernet PHYs232.2.5 Host Bus Interface (HBI)232.2.6 Host MAC242.2.7 EEPROM Controller/Loader242.2.8 1588 Time Stamp242.2.9 GPIO/LED Controller252.3 System Configuration25Figure 2.2 System Block Diagram25Chapter 3 Pin Description and Configuration263.1 Pin Diagrams263.1.1 128-VTQFP Pin Diagram26Figure 3.1 LAN9312 128-VTQFP Pin Assignments (TOP VIEW)263.1.2 128-XVTQFP Pin Diagram27Figure 3.2 LAN9312 128-XVTQFP Pin Assignments (TOP VIEW)273.2 Pin Descriptions28Table 3.1 LAN Port 1 Pins28Table 3.2 LAN Port 2 Pins29Table 3.3 LAN Port 1 & 2 Power and Common Pins29Table 3.4 Host Bus Interface Pins30Table 3.5 EEPROM Pins31Table 3.6 Dedicated Configuration Strap Pins32Table 3.7 Miscellaneous Pins33Table 3.8 PLL Pins34Table 3.9 Core and I/O Power and Ground Pins34Table 3.10 No-Connect Pins35Chapter 4 Clocking, Resets, and Power Management364.1 Clocks364.2 Resets36Table 4.1 Reset Sources and Affected LAN9312 Circuitry374.2.1 Chip-Level Resets374.2.1.1 Power-On Reset (POR)374.2.1.2 nRST Pin Reset384.2.2 Multi-Module Resets384.2.2.1 Digital Reset (DIGITAL_RST)384.2.2.2 Soft Reset (SRST)394.2.3 Single-Module Resets394.2.3.1 Port 2 PHY Reset394.2.3.2 Port 1 PHY Reset394.2.3.3 Virtual PHY Reset404.2.4 Configuration Straps404.2.4.1 Soft-Straps40Table 4.2 Soft-Strap Configuration Strap Definitions414.2.4.2 Hard-Straps45Table 4.3 Hard-Strap Configuration Strap Definitions464.3 Power Management46Figure 4.1 PME and PME_INT Signal Generation474.3.1 Port 1 & 2 PHY Power Management474.3.2 Host MAC Power Management48Chapter 5 System Interrupts495.1 Functional Overview495.2 Interrupt Sources49Figure 5.1 Functional Interrupt Register Hierarchy505.2.1 1588 Time Stamp Interrupts515.2.2 Switch Fabric Interrupts515.2.3 Ethernet PHY Interrupts525.2.4 GPIO Interrupts525.2.5 Host MAC Interrupts525.2.6 Power Management Interrupts535.2.7 General Purpose Timer Interrupt535.2.8 Software Interrupt545.2.9 Device Ready Interrupt54Chapter 6 Switch Fabric556.1 Functional Overview556.2 Switch Fabric CSRs556.2.1 Switch Fabric CSR Writes56Figure 6.1 Switch Fabric CSR Write Access Flow Diagram576.2.2 Switch Fabric CSR Reads57Figure 6.2 Switch Fabric CSR Read Access Flow Diagram586.2.3 Flow Control Enable Logic58Table 6.1 Switch Fabric Flow Control Enable Logic596.3 10/100 Ethernet MACs606.3.1 Receive MAC606.3.1.1 Receive Counters616.3.2 Transmit MAC626.3.2.1 Transmit Counters626.4 Switch Engine (SWE)636.4.1 MAC Address Lookup Table63Figure 6.3 ALR Table Entry Structure636.4.1.1 Learning/Aging/Migration646.4.1.2 Static Entries646.4.1.3 Multicast Pruning646.4.1.4 Address Filtering646.4.1.5 Spanning Tree Port State Override646.4.1.6 MAC Destination Address Lookup Priority646.4.1.7 Host Access646.4.2 Forwarding Rules666.4.3 Transmit Priority Queue Selection67Figure 6.4 Switch Engine Transmit Queue Selection67Figure 6.5 Switch Engine Transmit Queue Calculation686.4.3.1 Port Default Priority696.4.3.2 IP Precedence Based Priority696.4.3.3 DIFFSERV Based Priority696.4.3.4 VLAN Priority696.4.4 VLAN Support70Figure 6.6 VLAN Table Entry Structure706.4.5 Spanning Tree Support70Table 6.2 Spanning Tree States706.4.6 Ingress Flow Metering and Coloring71Table 6.3 Typical Ingress Rate Settings726.4.6.1 Ingress Flow Calculation72Figure 6.7 Switch Engine Ingress Flow Priority Selection73Figure 6.8 Switch Engine Ingress Flow Priority Calculation736.4.7 Broadcast Storm Control74Table 6.4 Typical Broadcast Rate Settings746.4.8 IPv4 IGMP / IPv6 MLD Support746.4.9 Port Mirroring756.4.10 Host CPU Port Special Tagging756.4.10.1 Packets from the Host CPU756.4.10.2 Packets to the Host CPU766.4.11 Counters766.5 Buffer Manager (BM)776.5.1 Packet Buffer Allocation776.5.1.1 Buffer Limits and Flow Control Levels776.5.2 Random Early Discard (RED)776.5.3 Transmit Queues776.5.4 Transmit Priority Queue Servicing786.5.5 Egress Rate Limiting (Leaky Bucket)78Table 6.5 Typical Egress Rate Settings786.5.6 Adding, Removing, and Changing VLAN Tags79Figure 6.9 Hybrid Port Tagging and Un-tagging806.5.7 Counters816.6 Switch Fabric Interrupts81Chapter 7 Ethernet PHYs827.1 Functional Overview827.1.1 PHY Addressing82Table 7.1 Default PHY Serial MII Addressing827.2 Port 1 & 2 PHYs83Figure 7.1 Port x PHY Block Diagram837.2.1 100BASE-TX Transmit84Figure 7.2 100BASE-TX Transmit Data Path847.2.1.1 MII MAC Interface847.2.1.2 4B/5B Encoder84Table 7.2 4B/5B Code Table857.2.1.3 Scrambler and PISO867.2.1.4 NRZI and MLT-3 Encoding867.2.1.5 100M Transmit Driver867.2.1.6 100M Phase Lock Loop (PLL)867.2.2 100BASE-TX Receive87Figure 7.3 100BASE-TX Receive Data Path877.2.2.1 A/D Converter877.2.2.2 DSP: Equalizer, BLW Correction and Clock/Data Recovery877.2.2.3 NRZI and MLT-3 Decoding887.2.2.4 Descrambler and SIPO887.2.2.5 5B/4B Decoding887.2.2.6 Receiver Errors887.2.2.7 MII MAC Interface887.2.3 10BASE-T Transmit897.2.3.1 MII MAC Interface897.2.3.2 10M TX Driver and PLL897.2.4 10BASE-T Receive897.2.4.1 Filter and Squelch897.2.4.2 10M RX and PLL897.2.4.3 MII MAC Interface907.2.4.4 Jabber Detection907.2.5 PHY Auto-negotiation907.2.5.1 PHY Pause Flow Control927.2.5.2 Parallel Detection927.2.5.3 Restarting Auto-Negotiation927.2.5.4 Disabling Auto-Negotiation927.2.5.5 Half Vs. Full-Duplex937.2.6 HP Auto-MDIX93Figure 7.4 Direct Cable Connection vs. Cross-Over Cable Connection937.2.7 MII MAC Interface937.2.8 PHY Management Control947.2.8.1 PHY Interrupts94Table 7.3 PHY Interrupt Sources947.2.9 PHY Power-Down Modes947.2.9.1 PHY General Power-Down957.2.9.2 PHY Energy Detect Power-Down957.2.10 PHY Resets957.2.10.1 PHY Software Reset via RESET_CTL957.2.10.2 PHY Software Reset via PHY_BASIC_CTRL_x967.2.10.3 PHY Power-Down Reset967.2.11 LEDs967.2.12 Required Ethernet Magnetics967.3 Virtual PHY967.3.1 Virtual PHY Auto-Negotiation967.3.1.1 Parallel Detection977.3.1.2 Disabling Auto-Negotiation977.3.1.3 Virtual PHY Pause Flow Control987.3.2 Virtual PHY Resets987.3.2.1 Virtual PHY Software Reset via RESET_CTL987.3.2.2 Virtual PHY Software Reset via VPHY_BASIC_CTRL987.3.2.3 Virtual PHY Software Reset via PMT_CTRL98Chapter 8 Host Bus Interface (HBI)998.1 Functional Overview998.2 Host Memory Mapping998.3 Host Endianess99Figure 8.1 Little Endian Byte Ordering100Figure 8.2 Big Endian Byte Ordering1008.4 Host Interface Timing1018.4.1 Special Situations1018.4.1.1 Reset Ending During a Read Cycle1018.4.1.2 Writes Following a Reset1018.4.2 Special Restrictions on Back-to Back Write-Read Cycles101Table 8.1 Read After Write Timing Rules1028.4.3 Special Restrictions on Back-to-Back Read Cycles105Table 8.2 Read After Read Timing Rules1058.4.4 PIO Reads106Figure 8.3 Functional Timing for PIO Read Operation1068.4.5 PIO Burst Reads107Figure 8.4 Functional Timing for PIO Burst Read Operation1078.4.6 RX Data FIFO Direct PIO Reads108Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation1088.4.7 RX Data FIFO Direct PIO Burst Reads109Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation1098.4.8 PIO Writes110Figure 8.7 Functional Timing for PIO Write Operation1108.4.9 TX Data FIFO Direct PIO Writes111Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation1118.5 HBI Interrupts111Chapter 9 Host MAC1129.1 Functional Overview1129.2 Flow Control1139.2.1 Full-Duplex Flow Control1139.2.2 Half-Duplex Flow Control (Backpressure)1139.3 Virtual Local Area Network (VLAN) Support113Figure 9.1 VLAN Frame1149.4 Address Filtering114Table 9.1 Address Filtering Modes1159.4.1 Perfect Filtering1159.4.2 Hash Only Filtering1159.4.3 Hash Perfect Filtering1159.4.4 Inverse Filtering1169.5 Wake-up Frame Detection116Table 9.2 Wake-Up Frame Filter Register Structure117Table 9.3 Filter i Byte Mask Bit Definitions117Table 9.4 Filter i Command Bit Definitions117Table 9.5 Filter i Offset Bit Definitions118Table 9.6 Filter i CRC-16 Bit Definitions1189.5.1 Magic Packet Detection1189.6 Host MAC Address119Table 9.7 EEPROM Byte Ordering and Register Correlation119Figure 9.2 Example EEPROM MAC Address Setup1209.7 FIFOs1209.7.1 TX/RX FIFOs1209.7.2 MIL FIFOs1209.7.3 FIFO Memory Allocation Configuration121Table 9.8 TX/RX FIFO Configurable Sizes121Table 9.9 Valid TX/RX FIFO Allocations1229.8 TX Data Path Operation122Figure 9.3 Simplified Host TX Flow Diagram1239.8.1 TX Buffer Format124Figure 9.4 TX Buffer Format1249.8.2 TX Command Format1249.8.2.1 TX Command ‘A’125Table 9.10 TX Command 'A' Format1259.8.2.2 TX Command ‘B’126Table 9.11 TX Command 'B' Format1269.8.3 TX Data Format126Table 9.12 TX DATA Start Offset1269.8.3.1 TX Buffer Fragmentation Rules1269.8.3.2 Calculating Worst-Case TX MIL FIFO Usage1279.8.4 TX Status Format1279.8.5 Calculating Actual TX Data FIFO Usage1289.8.6 Transmit Examples1289.8.6.1 TX Example 1128Figure 9.5 TX Example 11299.8.6.2 TX Example 2130Figure 9.6 TX Example 21309.8.7 Transmitter Errors1319.8.8 Stopping and Starting the Transmitter1319.9 RX Data Path Operation1329.9.1 RX Slave PIO Operation132Figure 9.7 Host Receive Routine Using Interrupts133Figure 9.8 Host Receive Routine Using Polling1339.9.1.1 Receive Data FIFO Fast Forward1349.9.1.2 Force Receiver Discard (Receiver Dump)1349.9.2 RX Packet Format134Figure 9.9 RX Packet Format1359.9.3 RX Status Format1359.9.4 Stopping and Starting the Receiver1369.9.5 Receiver Errors136Chapter 10 Serial Management13710.1 Functional Overview13710.2 I2C/Microwire Master EEPROM Controller137Table 10.1 I2C/Microwire Master Serial Management Pins Characteristics13710.2.1 EEPROM Controller Operation138Figure 10.1 EEPROM Access Flow Diagram13910.2.2 I2C EEPROM139Table 10.2 I2C EEPROM Size Ranges14010.2.2.1 I2C Protocol Overview140Figure 10.2 I2C Cycle14110.2.2.2 I2C EEPROM Device Addressing141Figure 10.3 I2C EEPROM Addressing14110.2.2.3 I2C EEPROM Byte Read142Figure 10.4 I2C EEPROM Byte Read14210.2.2.4 I2C EEPROM Sequential Byte Reads142Figure 10.5 I2C EEPROM Sequential Byte Reads14210.2.2.5 I2C EEPROM Byte Writes143Figure 10.6 I2C EEPROM Byte Write14310.2.3 Microwire EEPROM144Table 10.3 Microwire EEPROM Size Ranges14410.2.3.1 Microwire Master Commands144Table 10.4 Microwire Command Set for 7 Address Bits144Table 10.5 Microwire Command Set for 9 Address Bits144Table 10.6 Microwire Command Set for 11 Address Bits14510.2.3.2 ERASE (Erase Location)145Figure 10.7 EEPROM ERASE Cycle14510.2.3.3 ERAL (Erase All)146Figure 10.8 EEPROM ERAL Cycle14610.2.3.4 EWDS (Erase/Write Disable)146Figure 10.9 EEPROM EWDS Cycle14610.2.3.5 EWEN (Erase/Write Enable)147Figure 10.10 EEPROM EWEN Cycle14710.2.3.6 READ (Read Location)147Figure 10.11 EEPROM READ Cycle14710.2.3.7 WRITE (Write Location)148Figure 10.12 EEPROM WRITE Cycle14810.2.3.8 WRAL (Write All)148Figure 10.13 EEPROM WRAL Cycle14810.2.4 EEPROM Loader149Table 10.7 EEPROM Contents Format Overview14910.2.4.1 EEPROM Loader Operation149Figure 10.14 EEPROM Loader Flow Diagram15010.2.4.2 EEPROM Valid Flag15110.2.4.3 MAC Address15110.2.4.3.1 Host MAC Address Reload15110.2.4.4 Soft-Straps151Table 10.8 EEPROM Configuration Bits15110.2.4.4.1 PHY Registers Synchronization15110.2.4.4.2 Virtual PHY Registers Synchronization15210.2.4.4.3 LED and Manual Flow Control Register Synchronization15210.2.4.5 Register Data15210.2.4.6 EEPROM Loader Finished Wait-State15310.2.4.7 Reset Sequence and EEPROM Loader153Chapter 11 IEEE 1588 Hardware Time Stamp Unit15411.1 Functional Overview15411.1.1 IEEE 158815411.1.2 Block Diagram155Figure 11.1 IEEE 1588 Block Diagram15511.2 IEEE 1588 Time Stamp156Table 11.1 IEEE 1588 Message Type Detection156Figure 11.2 IEEE 1588 Message Time Stamp Point156Table 11.2 Time Stamp Capture Delay15711.2.1 Capture Locking15711.2.2 PTP Message Detection158Table 11.3 PTP Multicast Addresses15811.3 IEEE 1588 Clock159Table 11.4 Typical IEEE 1588 Clock Addend Values15911.4 IEEE 1588 Clock/Events16011.5 IEEE 1588 GPIOs16011.6 IEEE 1588 Interrupts160Chapter 12 General Purpose Timer & Free-Running Clock16112.1 General Purpose Timer16112.2 Free-Running Clock161Chapter 13 GPIO/LED Controller16213.1 Functional Overview16213.2 GPIO Operation16213.2.1 GPIO IEEE 1588 Timestamping16313.2.1.1 IEEE 1588 GPIO Inputs16313.2.1.2 IEEE 1588 GPIO Outputs16313.2.2 GPIO Interrupts16313.2.2.1 GPIO Interrupt Polarity16313.2.2.2 IEEE 1588 GPIO Interrupts16413.3 LED Operation164Table 13.1 LED Operation as a Function of LED_CFG[9:8]164Chapter 14 Register Descriptions166Figure 14.1 LAN9312 Base Register Memory Map16614.1 TX/RX FIFO Ports16714.1.1 TX/RX Data FIFO’s16714.1.2 TX/RX Status FIFO’s16714.1.3 Direct FIFO Access Mode16714.2 System Control and Status Registers168Table 14.1 System Control and Status Registers16814.2.1 Interrupts17214.2.1.1 Interrupt Configuration Register (IRQ_CFG)17214.2.1.2 Interrupt Status Register (INT_STS)17414.2.1.3 Interrupt Enable Register (INT_EN)17714.2.1.4 FIFO Level Interrupt Register (FIFO_INT)17914.2.2 Host MAC & FIFO’s18014.2.2.1 Receive Configuration Register (RX_CFG)18014.2.2.2 Transmit Configuration Register (TX_CFG)18214.2.2.3 Receive Datapath Control Register (RX_DP_CTRL)18314.2.2.4 RX FIFO Information Register (RX_FIFO_INF)18414.2.2.5 TX FIFO Information Register (TX_FIFO_INF)18514.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP)18614.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)18714.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA)18814.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG)189Table 14.2 Backpressure Duration Bit Mapping19014.2.3 GPIO/LED19214.2.3.1 General Purpose I/O Configuration Register (GPIO_CFG)19214.2.3.2 General Purpose I/O Data & Direction Register (GPIO_DATA_DIR)19414.2.3.3 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)19514.2.3.4 LED Configuration Register (LED_CFG)19614.2.4 EEPROM19714.2.4.1 EEPROM Command Register (E2P_CMD)19714.2.4.2 EEPROM Data Register (E2P_DATA)20014.2.5 IEEE 158820114.2.5.1 Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x)20114.2.5.2 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x)20214.2.5.3 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)20314.2.5.4 Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)20414.2.5.5 Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x)20514.2.5.6 Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x)20614.2.5.7 Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x)20714.2.5.8 Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x)20814.2.5.9 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8)20914.2.5.10 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8)21014.2.5.11 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9)21114.2.5.12 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9)21214.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI)21314.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO)21414.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND)21514.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)21614.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO)21714.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI)21814.2.5.19 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO)21914.2.5.20 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI)22014.2.5.21 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO)22114.2.5.22 1588 Configuration Register (1588_CONFIG)22214.2.5.23 1588 Interrupt Status and Enable Register (1588_INT_STS_EN)22614.2.5.24 1588 Command Register (1588_CMD)22814.2.6 Switch Fabric22914.2.6.1 Port 1 Manual Flow Control Register (MANUAL_FC_1)22914.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2)23114.2.6.3 Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII)23314.2.6.4 Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA)23514.2.6.5 Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD)23614.2.6.6 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH)23814.2.6.7 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL)23914.2.6.8 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA)240Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map24014.2.7 PHY Management Interface (PMI)24314.2.7.1 PHY Management Interface Data Register (PMI_DATA)24314.2.7.2 PHY Management Interface Access Register (PMI_ACCESS)24414.2.8 Virtual PHY245Table 14.4 Virtual PHY MII Serially Adressable Register Index24514.2.8.1 Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)24614.2.8.2 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)24814.2.8.3 Virtual PHY Identification MSB Register (VPHY_ID_MSB)25014.2.8.4 Virtual PHY Identification LSB Register (VPHY_ID_LSB)25114.2.8.5 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)25214.2.8.6 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY)254Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values25514.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)25614.2.8.8 Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS)25714.2.9 Miscellaneous25914.2.9.1 Chip ID and Revision (ID_REV)25914.2.9.2 Byte Order Test Register (BYTE_TEST)26014.2.9.3 Hardware Configuration Register (HW_CFG)26114.2.9.4 Power Management Control Register (PMT_CTRL)26314.2.9.5 General Purpose Timer Configuration Register (GPT_CFG)26514.2.9.6 General Purpose Timer Count Register (GPT_CNT)26614.2.9.7 Free Running 25MHz Counter Register (FREE_RUN)26714.2.9.8 Reset Control Register (RESET_CTL)26814.3 Host MAC Control and Status Registers269Table 14.6 Host MAC Adressable Registers26914.3.1 Host MAC Control Register (HMAC_CR)27014.3.2 Host MAC Address High Register (HMAC_ADDRH)27314.3.3 Host MAC Address Low Register (HMAC_ADDRL)27414.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH)27514.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL)27614.3.6 Host MAC MII Access Register (HMAC_MII_ACC)27714.3.7 Host MAC MII Data Register (HMAC_MII_DATA)27814.3.8 Host MAC Flow Control Register (HMAC_FLOW)27914.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1)28114.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2)28214.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF)28314.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR)28414.4 Ethernet PHY Control and Status Registers28514.4.1 Virtual PHY Registers28514.4.2 Port 1 & 2 PHY Registers285Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers28514.4.2.1 Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)28714.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x)28914.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x)29114.4.2.4 Port x PHY Identification LSB Register (PHY_ID_LSB_x)29214.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)293Table 14.8 10BASE-T Full Duplex Advertisement Default Value294Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value29414.4.2.6 Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x)29614.4.2.7 Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x)29814.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)29914.4.2.9 Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)300Table 14.10 MODE[2:0] Definitions30014.4.2.10 Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x)302Table 14.11 Auto-MDIX Enable and Auto-MDIX State Bit Functionality30314.4.2.11 Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)30414.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x)30514.4.2.13 Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x)30614.5 Switch Fabric Control and Status Registers307Table 14.12 Indirectly Accessible Switch Control and Status Registers30714.5.1 General Switch CSRs31814.5.1.1 Switch Device ID Register (SW_DEV_ID)31814.5.1.2 Switch Reset Register (SW_RESET)31914.5.1.3 Switch Global Interrupt Mask Register (SW_IMR)32014.5.1.4 Switch Global Interrupt Pending Register (SW_IPR)32114.5.2 Switch Port 0, Port 1, and Port 2 CSRs32214.5.2.1 Port x MAC Version ID Register (MAC_VER_ID_x)32214.5.2.2 Port x MAC Receive Configuration Register (MAC_RX_CFG_x)32314.5.2.3 Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x)32414.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x)32514.5.2.5 Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)32614.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)32714.5.2.7 Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)32814.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)32914.5.2.9 Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x)33014.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x)33114.5.2.11 Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)33214.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x)33314.5.2.13 Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x)33414.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x)33514.5.2.15 Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x)33614.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)33714.5.2.17 Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x)33814.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x)33914.5.2.19 Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x)34014.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x)34114.5.2.21 Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x)34214.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x)34314.5.2.23 Port x MAC Transmit Configuration Register (MAC_TX_CFG_x)34414.5.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x)34514.5.2.25 Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x)34614.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x)34714.5.2.27 Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x)34814.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x)34914.5.2.29 Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x)35014.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x)35114.5.2.31 Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x)35214.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x)35314.5.2.33 Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)35414.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x)35514.5.2.35 Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x)35614.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x)35714.5.2.37 Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x)35814.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x)35914.5.2.39 Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)36014.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x)36114.5.2.41 Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x)36214.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)36314.5.2.43 Port x MAC Interrupt Mask Register (MAC_IMR_x)36414.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x)36514.5.3 Switch Engine CSRs36614.5.3.1 Switch Engine ALR Command Register (SWE_ALR_CMD)36614.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)36714.5.3.3 Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)36814.5.3.4 Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)37014.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)37114.5.3.6 Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS)37314.5.3.7 Switch Engine ALR Configuration Register (SWE_ALR_CFG)37414.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD)37514.5.3.9 Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA)37614.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA)37714.5.3.11 Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS)37814.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)37914.5.3.13 Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)38014.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA)38114.5.3.15 Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS)38214.5.3.16 Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)38314.5.3.17 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG)38514.5.3.18 Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)38614.5.3.19 Switch Engine Port State Register (SWE_PORT_STATE)38714.5.3.20 Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)38814.5.3.21 Switch Engine Port Mirroring Register (SWE_PORT_MIRROR)38914.5.3.22 Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP)39014.5.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT)39114.5.3.24 Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)39214.5.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG)39314.5.3.26 Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)39414.5.3.26.1 Ingress Rate Table Registers395Table 14.13 Metering/Color Table Register Descriptions39514.5.3.27 Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS)39614.5.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)39714.5.3.29 Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA)39814.5.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII)39914.5.3.31 Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1)40014.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2)40114.5.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII)40214.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1)40314.5.3.35 Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2)40414.5.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII)40514.5.3.37 Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1)40614.5.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2)40714.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR)40814.5.3.40 Switch Engine Interrupt Pending Register (SWE_IPR)40914.5.4 Buffer Manager CSRs41114.5.4.1 Buffer Manager Configuration Register (BM_CFG)41114.5.4.2 Buffer Manager Drop Level Register (BM_DROP_LVL)41214.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)41314.5.4.4 Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL)41414.5.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)41514.5.4.6 Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII)41614.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1)41714.5.4.8 Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2)41814.5.4.9 Buffer Manager Reset Status Register (BM_RST_STS)41914.5.4.10 Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)42014.5.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA)42114.5.4.12 Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)42214.5.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE)42314.5.4.14 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01)42514.5.4.15 Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03)42614.5.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11)42714.5.4.17 Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13)42814.5.4.18 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21)42914.5.4.19 Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23)43014.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII)43114.5.4.21 Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1)43214.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2)43314.5.4.23 Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII)43414.5.4.24 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1)43514.5.4.25 Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2)43614.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR)43714.5.4.27 Buffer Manager Interrupt Pending Register (BM_IPR)438Chapter 15 Operational Characteristics44015.1 Absolute Maximum Ratings*44015.2 Operating Conditions**44015.3 Power Consumption441Table 15.1 Supply and Current (10BASE-T Full-Duplex)441Table 15.2 Supply and Current (100BASE-TX Full-Duplex)44115.4 DC Specifications442Table 15.3 I/O Buffer Characteristics442Table 15.4 100BASE-TX Transceiver Characteristics442Table 15.5 10BASE-T Transceiver Characteristics44315.5 AC Specifications44315.5.1 Equivalent Test Load443Figure 15.1 Output Equivalent Test Load44315.5.2 Reset and Configuration Strap Timing444Figure 15.2 nRST Reset Pin Timing444Table 15.6 nRST Reset Pin Timing Values44415.5.3 Power-On Configuration Strap Valid Timing445Figure 15.3 Power-On Configuration Strap Latching Timing445Table 15.7 Power-On Configuration Strap Latching Timing Values44515.5.4 PIO Read Cycle Timing446Figure 15.4 PIO Read Cycle Timing446Table 15.8 PIO Read Cycle Timing Values44615.5.5 PIO Burst Read Cycle Timing447Figure 15.5 PIO Burst Read Cycle Timing447Table 15.9 PIO Burst Read Cycle Timing Values44715.5.6 RX Data FIFO Direct PIO Read Cycle Timing448Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing448Table 15.10 RX Data FIFO Direct PIO Read Cycle Timing Values44815.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing449Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing449Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values44915.5.8 PIO Write Cycle Timing450Figure 15.8 PIO Write Cycle Timing450Table 15.12 PIO Write Cycle Timing Values45015.5.9 TX Data FIFO Direct PIO Write Cycle Timing451Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing451Table 15.13 TX Data FIFO Direct PIO Write Cycle Timing Values45115.5.10 Microwire Timing452Figure 15.10 Microwire Timing452Table 15.14 Microwire Timing Values45215.6 Clock Circuit453Table 15.15 LAN9312Crystal Specifications453Chapter 16 Package Outlines45416.1 128-VTQFP Package Outline454Figure 16.1 LAN9312 128-VTQFP Package Definition454Table 16.1 LAN9312 128-VTQFP Dimensions454Figure 16.2 LAN9312 128-VTQFP Recommended PCB Land Pattern45516.2 128-XVTQFP Package Outline456Figure 16.3 LAN9312 128-XVTQFP Package Definition456Table 16.2 LAN9312 128-XVTQFP Dimensions457Figure 16.4 LAN9312 128-XVTQFP Recommended PCB Land Pattern457Chapter 17 Revision History458Table 17.1 Customer Revision History458Size: 4.75 MBPages: 458Language: EnglishOpen manual