User ManualTable of ContentsChapter 1 Introduction111.1 Block Diagrams11Figure 1.1 System Level Block Diagram11Figure 1.2 LAN9420/LAN9420i Internal Block Diagram111.2 General Description121.3 PCI Bridge131.4 DMA Controller131.5 Ethernet MAC131.6 Ethernet PHY131.7 System Control Block131.7.1 Interrupt Controller131.7.2 PLL and Power Management141.7.3 EEPROM Controller141.7.4 GPIO/LED Controller141.7.5 General Purpose Timer141.7.6 Free Run Counter141.8 Control and Status Registers (CSR)14Chapter 2 Pin Description and Configuration15Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View)152.1 Pin List16Table 2.1 PCI Bus Interface Pins16Table 2.2 EEPROM17Table 2.3 GPIO and LED Pins18Table 2.4 Configuration Pins18Table 2.5 PLL and Ethernet PHY Pins19Table 2.6 Power and Ground Pins20Table 2.7 No-Connect Pins20Table 2.8 128-VTQFP Package Pin Assignments212.2 Buffer Types22Chapter 3 Functional Description233.1 Functional Overview233.2 PCI Bridge (PCIB)233.2.1 PCI Bridge (PCIB) Block Diagram24Figure 3.1 PCI Bridge Block Diagram243.2.2 PCI Interface Environments25Figure 3.2 Device Operation253.2.3 PCI Master Interface253.2.4 PCI Target Interface26Table 3.1 PCI Address Spaces26Figure 3.3 CSR Double Endian Mapping27Figure 3.4 I/O Bar Mapping273.2.5 Interrupt Gating Logic27Figure 3.5 Interrupt Generation283.3 System Control Block (SCB)283.3.1 Interrupt Controller28Figure 3.6 Interrupt Controller Block Diagram293.3.2 Wake Event Detection Logic303.3.3 General Purpose Timer (GPT)303.3.4 Free-Run Counter (FRC)313.3.5 EEPROM Controller (EPC)31Table 3.2 EEPROM Format31Table 3.3 EEPROM Variable Defaults32Figure 3.7 EEPROM Access Flow Diagram33Figure 3.8 EEPROM ERASE Cycle34Figure 3.9 EEPROM ERAL Cycle34Figure 3.10 EEPROM EWDS Cycle35Figure 3.11 EEPROM EWEN Cycle35Figure 3.12 EEPROM READ Cycle36Figure 3.13 EEPROM WRITE Cycle36Figure 3.14 EEPROM WRAL Cycle37Table 3.4 Required EECLK Cycles373.3.6 System Control and Status Registers (SCSR)383.4 DMA Controller (DMAC)383.4.1 DMA Controller Architecture383.4.2 Data Descriptors and Buffers38Figure 3.15 Ring and Chain Descriptor Structures40Figure 3.16 Receive Descriptor41Table 3.5 RDES0 Bit Fields41Table 3.6 RDES1 Bit Fields44Table 3.7 RDES2 Bit Fields44Table 3.8 RDES3 Bit Fields45Figure 3.17 Transmit Descriptor45Table 3.9 TDES0 Bit Fields46Table 3.10 TDES1 Bit Fields47Table 3.11 TDES2 Bit Fields49Table 3.12 TDES3 Bit Fields493.4.3 Initialization493.4.4 Transmit Operation503.4.5 Receive Operation503.4.6 Receive Descriptor Acquisition503.4.7 Suspend State Behavior513.4.8 Stopping Transmission and Reception513.4.9 TX Buffer Fragmentation Rules523.4.10 DMAC Interrupts523.4.11 DMAC Control and Status Registers (DCSR)523.5 10/100 Ethernet MAC533.5.1 Flow Control543.5.2 Virtual Local Area Network (VLAN) Support54Figure 3.18 VLAN Frame553.5.3 Address Filtering Functional Description55Table 3.13 Address Filtering Modes553.5.4 Wakeup Frame Detection57Table 3.14 Wakeup Frame Filter Register Structure57Table 3.15 Filter i Byte Mask Bit Definitions58Table 3.16 Filter i Command Bit Definitions58Table 3.17 Filter i Offset Bit Definitions58Table 3.18 Filter i CRC-16 Bit Definitions59Table 3.19 Wakeup Generation Cases593.5.5 Receive Checksum Offload Engine (RXCOE)60Figure 3.19 RXCOE Checksum Calculation60Figure 3.20 Type II Ethernet Frame61Figure 3.21 Ethernet Frame with VLAN Tag61Figure 3.22 Ethernet Frame with Length Field and SNAP Header61Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header62Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP Header623.5.6 Transmit Checksum Offload Engine (TXCOE)63Table 3.20 TX Checksum Preamble633.5.7 MAC Control and Status Registers (MCSR)643.6 10/100 Ethernet PHY64Figure 3.25 100BASE-TX Data Path653.6.1 100BASE-TX Transmit65Table 3.21 4B/5B Code Table65Figure 3.26 Receive Data Path673.6.2 100BASE-TX Receive673.6.3 10BASE-T Transmit693.6.4 10BASE-T Receive693.6.5 Auto-negotiation703.6.6 Parallel Detection713.6.7 HP Auto-MDIX72Figure 3.27 Direct Cable Connection vs. Cross-Over Cable Connection723.6.8 PHY Power-Down Modes723.6.9 PHY Resets733.6.10 Required Ethernet Magnetics733.6.11 PHY Registers733.7 Power Management733.7.1 Overview733.7.2 Related External Signals and Power Supplies743.7.3 Device Clocking753.7.4 Power States75Figure 3.28 LAN9420/LAN9420i Device Power States753.7.5 Resets79Table 3.22 Reset Map79Table 3.23 PHY Resets803.7.6 Detecting Power Management Events80Figure 3.29 Wake Event Detection Block Diagram803.7.7 Enabling Link Status Change (Energy Detect) Wake Events81Chapter 4 Register Descriptions83Figure 4.1 LAN9420/LAN9420i CSR Memory Map844.1 Register Nomenclature85Table 4.1 Register Bit Types854.2 System Control and Status Registers (SCSR)86Table 4.2 System Control and Status Register Addresses864.2.1 ID and Revision (ID_REV)874.2.2 Interrupt Control Register (INT_CTL)884.2.3 Interrupt Status Register (INT_STS)894.2.4 Interrupt Configuration Register (INT_CFG)914.2.5 General Purpose Input/Output Configuration Register (GPIO_CFG)92Table 4.3 EEPROM Enable Bit Definitions934.2.6 General Purpose Timer Configuration Register (GPT_CFG)944.2.7 General Purpose Timer Current Count Register (GPT_CNT)954.2.8 Bus Master Bridge Configuration Register (BUS_CFG)964.2.9 Power Management Control Register (PMT_CTRL)974.2.10 Free Run Counter (FREE_RUN)984.2.11 EEPROM Command Register (E2P_CMD)994.2.12 EEPROM Data Register (E2P_DATA)1024.3 DMAC Control and Status Registers (DCSR)103Table 4.4 DMAC Control and Status Register (DCSR) Map1034.3.1 Bus Mode Register (BUS_MODE)1044.3.2 Transmit Poll Demand Register (TX_POLL_DEMAND)1054.3.3 Receive Poll Demand Register (RX_POLL_DEMAND)1064.3.4 Receive List Base Address Register (RX_BASE_ADDR)1074.3.5 Transmit List Base Address Register (TX_BASE_ADDR)1084.3.6 DMA Controller Status Register (DMAC_STATUS)1094.3.7 DMA Controller Control (Operation Mode) Register (DMAC_CONTROL)1114.3.8 DMA Controller Interrupt Enable Register (DMAC_INTR_ENA)1134.3.9 Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)1154.3.10 Current Transmit Buffer Address Register (TX_BUFF_ADDR)1164.3.11 Current Receive Buffer Address Register (RX_BUFF_ADDR)1174.4 MAC Control and Status Registers (MCSR)118Table 4.5 MAC Control and Status Register (MCSR) Map1184.4.1 MAC Control Register (MAC_CR)1194.4.2 MAC Address High Register (ADDRH)1234.4.3 MAC Address Low Register (ADDRL)124Table 4.6 ADDRL, ADDRH Byte Ordering124Figure 4.2 Example ADDRL, ADDRH Address Ordering1244.4.4 Multicast Hash Table High Register (HASHH)1254.4.5 Multicast Hash Table Low Register (HASHL)1264.4.6 MII Access Register (MII_ACCESS)1274.4.7 MII Data Register (MII_DATA)1284.4.8 Flow Control Register (FLOW)1294.4.9 VLAN1 Tag Register (VLAN1)1304.4.10 VLAN2 Tag Register (VLAN2)1314.4.11 Wakeup Frame Filter (WUFF)1324.4.12 Wakeup Control and Status Register (WUCSR)1334.4.13 Checksum Offload Engine Control Register (COE_CR)1344.5 PHY Registers135Table 4.7 PHY Control and Status Registers1354.5.1 Basic Control Register1364.5.2 Basic Status Register1374.5.3 PHY Identifier 11384.5.4 PHY Identifier 21394.5.5 Auto Negotiation Advertisement1404.5.6 Auto Negotiation Link Partner Ability1414.5.7 Auto Negotiation Expansion1424.5.8 Mode Control/Status1434.5.9 Special Modes144Table 4.8 MODE Control1444.5.10 Special Control/Status Indications1454.5.11 Interrupt Source Flag1464.5.12 Interrupt Mask1474.5.13 PHY Special Control/Status1484.6 PCI Configuration Space CSR (CONFIG CSR)149Table 4.9 PCI Configuration Space CSR (CONFIG CSR) Address Map149Table 4.10 Standard PCI Header Registers Supported1504.6.1 PCI Power Management Capabilities Register (PCI_PMC)1514.6.2 PCI Power Management Control and Status Register (PCI_PMCSR)153Chapter 5 Operational Characteristics1555.1 Absolute Maximum Ratings*1555.2 Operating Conditions**1555.3 Power Consumption1565.3.1 D0 - Normal Operation with Ethernet Traffic156Table 5.1 D0 - Normal Operation - Supply and Current (Typical)1565.3.2 D3 - Enabled for Wake Up Packet Detection157Table 5.2 D3 - Enabled for Wake Up Packet Detection - Supply and Current (Typical)1575.3.3 D3 - Enabled for Link Status Change Detection (Energy Detect)157Table 5.3 D3 - Enabled for Link Status Change Detection - Supply and Current (Typical)1575.3.4 D3 - PHY in General Power Down Mode158Table 5.4 D3 - PHY in General Power Down Mode - Supply and Current (Typical)1585.3.5 Maximum Power Consumption158Table 5.5 Maximum Power Consumption - Supply and Current (Maximum)1585.4 DC Specifications159Table 5.6 I/O Buffer Characteristics159Table 5.7 100BASE-TX Transceiver Characteristics160Table 5.8 10BASE-T Transceiver Characteristics1605.5 AC Specifications1615.5.1 Equivalent Test Load (Non-PCI Signals)161Figure 5.1 Output Equivalent Test Load1615.6 PCI Clock Timing162Figure 5.2 PCI Clock Timing162Table 5.9 PCI Clock Timing Values1625.7 PCI I/O Timing163Figure 5.3 PCI I/O Timing163Table 5.10 PCI I/O Timing Measurement Conditions163Table 5.11 PCI I/O Timing Values1645.8 EEPROM Timing165Figure 5.4 EEPROM Timing165Table 5.12 EEPROM Timing Values1655.9 Clock Circuit166Table 5.13 LAN9420/LAN9420i Crystal Specifications166Chapter 6 Package Outline1676.1 128-VTQFP Package167Figure 6.1 LAN9420/LAN9420i 128-VTQFP Package Definition167Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions168Figure 6.2 LAN9420/LAN9420i 128-VTQFP Recommended PCB Land Pattern168Chapter 7 Revision History169Table 7.1 Customer Revision History169Size: 1.74 MBPages: 169Language: EnglishOpen manual
User ManualTable of ContentsChapter 1 Introduction111.1 Block Diagrams11Figure 1.1 System Level Block Diagram11Figure 1.2 LAN9420/LAN9420i Internal Block Diagram111.2 General Description121.3 PCI Bridge131.4 DMA Controller131.5 Ethernet MAC131.6 Ethernet PHY131.7 System Control Block131.7.1 Interrupt Controller131.7.2 PLL and Power Management141.7.3 EEPROM Controller141.7.4 GPIO/LED Controller141.7.5 General Purpose Timer141.7.6 Free Run Counter141.8 Control and Status Registers (CSR)14Chapter 2 Pin Description and Configuration15Figure 2.1 LAN9420/LAN9420i 128-VTQFP (Top View)152.1 Pin List16Table 2.1 PCI Bus Interface Pins16Table 2.2 EEPROM17Table 2.3 GPIO and LED Pins18Table 2.4 Configuration Pins18Table 2.5 PLL and Ethernet PHY Pins19Table 2.6 Power and Ground Pins20Table 2.7 No-Connect Pins20Table 2.8 128-VTQFP Package Pin Assignments212.2 Buffer Types22Chapter 3 Functional Description233.1 Functional Overview233.2 PCI Bridge (PCIB)233.2.1 PCI Bridge (PCIB) Block Diagram24Figure 3.1 PCI Bridge Block Diagram243.2.2 PCI Interface Environments25Figure 3.2 Device Operation253.2.3 PCI Master Interface253.2.4 PCI Target Interface26Table 3.1 PCI Address Spaces26Figure 3.3 CSR Double Endian Mapping27Figure 3.4 I/O Bar Mapping273.2.5 Interrupt Gating Logic27Figure 3.5 Interrupt Generation283.3 System Control Block (SCB)283.3.1 Interrupt Controller28Figure 3.6 Interrupt Controller Block Diagram293.3.2 Wake Event Detection Logic303.3.3 General Purpose Timer (GPT)303.3.4 Free-Run Counter (FRC)313.3.5 EEPROM Controller (EPC)31Table 3.2 EEPROM Format31Table 3.3 EEPROM Variable Defaults32Figure 3.7 EEPROM Access Flow Diagram33Figure 3.8 EEPROM ERASE Cycle34Figure 3.9 EEPROM ERAL Cycle34Figure 3.10 EEPROM EWDS Cycle35Figure 3.11 EEPROM EWEN Cycle35Figure 3.12 EEPROM READ Cycle36Figure 3.13 EEPROM WRITE Cycle36Figure 3.14 EEPROM WRAL Cycle37Table 3.4 Required EECLK Cycles373.3.6 System Control and Status Registers (SCSR)383.4 DMA Controller (DMAC)383.4.1 DMA Controller Architecture383.4.2 Data Descriptors and Buffers38Figure 3.15 Ring and Chain Descriptor Structures40Figure 3.16 Receive Descriptor41Table 3.5 RDES0 Bit Fields41Table 3.6 RDES1 Bit Fields44Table 3.7 RDES2 Bit Fields44Table 3.8 RDES3 Bit Fields45Figure 3.17 Transmit Descriptor45Table 3.9 TDES0 Bit Fields46Table 3.10 TDES1 Bit Fields47Table 3.11 TDES2 Bit Fields49Table 3.12 TDES3 Bit Fields493.4.3 Initialization493.4.4 Transmit Operation503.4.5 Receive Operation503.4.6 Receive Descriptor Acquisition503.4.7 Suspend State Behavior513.4.8 Stopping Transmission and Reception513.4.9 TX Buffer Fragmentation Rules523.4.10 DMAC Interrupts523.4.11 DMAC Control and Status Registers (DCSR)523.5 10/100 Ethernet MAC533.5.1 Flow Control543.5.2 Virtual Local Area Network (VLAN) Support54Figure 3.18 VLAN Frame553.5.3 Address Filtering Functional Description55Table 3.13 Address Filtering Modes553.5.4 Wakeup Frame Detection57Table 3.14 Wakeup Frame Filter Register Structure57Table 3.15 Filter i Byte Mask Bit Definitions58Table 3.16 Filter i Command Bit Definitions58Table 3.17 Filter i Offset Bit Definitions58Table 3.18 Filter i CRC-16 Bit Definitions59Table 3.19 Wakeup Generation Cases593.5.5 Receive Checksum Offload Engine (RXCOE)60Figure 3.19 RXCOE Checksum Calculation60Figure 3.20 Type II Ethernet Frame61Figure 3.21 Ethernet Frame with VLAN Tag61Figure 3.22 Ethernet Frame with Length Field and SNAP Header61Figure 3.23 Ethernet Frame with VLAN Tag and SNAP Header62Figure 3.24 Ethernet Frame with multiple VLAN Tags and SNAP Header623.5.6 Transmit Checksum Offload Engine (TXCOE)63Table 3.20 TX Checksum Preamble633.5.7 MAC Control and Status Registers (MCSR)643.6 10/100 Ethernet PHY64Figure 3.25 100BASE-TX Data Path653.6.1 100BASE-TX Transmit65Table 3.21 4B/5B Code Table65Figure 3.26 Receive Data Path673.6.2 100BASE-TX Receive673.6.3 10BASE-T Transmit693.6.4 10BASE-T Receive693.6.5 Auto-negotiation703.6.6 Parallel Detection713.6.7 HP Auto-MDIX72Figure 3.27 Direct Cable Connection vs. Cross-Over Cable Connection723.6.8 PHY Power-Down Modes723.6.9 PHY Resets733.6.10 Required Ethernet Magnetics733.6.11 PHY Registers733.7 Power Management733.7.1 Overview733.7.2 Related External Signals and Power Supplies743.7.3 Device Clocking753.7.4 Power States75Figure 3.28 LAN9420/LAN9420i Device Power States753.7.5 Resets79Table 3.22 Reset Map79Table 3.23 PHY Resets803.7.6 Detecting Power Management Events80Figure 3.29 Wake Event Detection Block Diagram803.7.7 Enabling Link Status Change (Energy Detect) Wake Events81Chapter 4 Register Descriptions83Figure 4.1 LAN9420/LAN9420i CSR Memory Map844.1 Register Nomenclature85Table 4.1 Register Bit Types854.2 System Control and Status Registers (SCSR)86Table 4.2 System Control and Status Register Addresses864.2.1 ID and Revision (ID_REV)874.2.2 Interrupt Control Register (INT_CTL)884.2.3 Interrupt Status Register (INT_STS)894.2.4 Interrupt Configuration Register (INT_CFG)914.2.5 General Purpose Input/Output Configuration Register (GPIO_CFG)92Table 4.3 EEPROM Enable Bit Definitions934.2.6 General Purpose Timer Configuration Register (GPT_CFG)944.2.7 General Purpose Timer Current Count Register (GPT_CNT)954.2.8 Bus Master Bridge Configuration Register (BUS_CFG)964.2.9 Power Management Control Register (PMT_CTRL)974.2.10 Free Run Counter (FREE_RUN)984.2.11 EEPROM Command Register (E2P_CMD)994.2.12 EEPROM Data Register (E2P_DATA)1024.3 DMAC Control and Status Registers (DCSR)103Table 4.4 DMAC Control and Status Register (DCSR) Map1034.3.1 Bus Mode Register (BUS_MODE)1044.3.2 Transmit Poll Demand Register (TX_POLL_DEMAND)1054.3.3 Receive Poll Demand Register (RX_POLL_DEMAND)1064.3.4 Receive List Base Address Register (RX_BASE_ADDR)1074.3.5 Transmit List Base Address Register (TX_BASE_ADDR)1084.3.6 DMA Controller Status Register (DMAC_STATUS)1094.3.7 DMA Controller Control (Operation Mode) Register (DMAC_CONTROL)1114.3.8 DMA Controller Interrupt Enable Register (DMAC_INTR_ENA)1134.3.9 Missed Frame and Buffer Overflow Counter Reg (MISS_FRAME_CNTR)1154.3.10 Current Transmit Buffer Address Register (TX_BUFF_ADDR)1164.3.11 Current Receive Buffer Address Register (RX_BUFF_ADDR)1174.4 MAC Control and Status Registers (MCSR)118Table 4.5 MAC Control and Status Register (MCSR) Map1184.4.1 MAC Control Register (MAC_CR)1194.4.2 MAC Address High Register (ADDRH)1234.4.3 MAC Address Low Register (ADDRL)124Table 4.6 ADDRL, ADDRH Byte Ordering124Figure 4.2 Example ADDRL, ADDRH Address Ordering1244.4.4 Multicast Hash Table High Register (HASHH)1254.4.5 Multicast Hash Table Low Register (HASHL)1264.4.6 MII Access Register (MII_ACCESS)1274.4.7 MII Data Register (MII_DATA)1284.4.8 Flow Control Register (FLOW)1294.4.9 VLAN1 Tag Register (VLAN1)1304.4.10 VLAN2 Tag Register (VLAN2)1314.4.11 Wakeup Frame Filter (WUFF)1324.4.12 Wakeup Control and Status Register (WUCSR)1334.4.13 Checksum Offload Engine Control Register (COE_CR)1344.5 PHY Registers135Table 4.7 PHY Control and Status Registers1354.5.1 Basic Control Register1364.5.2 Basic Status Register1374.5.3 PHY Identifier 11384.5.4 PHY Identifier 21394.5.5 Auto Negotiation Advertisement1404.5.6 Auto Negotiation Link Partner Ability1414.5.7 Auto Negotiation Expansion1424.5.8 Mode Control/Status1434.5.9 Special Modes144Table 4.8 MODE Control1444.5.10 Special Control/Status Indications1454.5.11 Interrupt Source Flag1464.5.12 Interrupt Mask1474.5.13 PHY Special Control/Status1484.6 PCI Configuration Space CSR (CONFIG CSR)149Table 4.9 PCI Configuration Space CSR (CONFIG CSR) Address Map149Table 4.10 Standard PCI Header Registers Supported1504.6.1 PCI Power Management Capabilities Register (PCI_PMC)1514.6.2 PCI Power Management Control and Status Register (PCI_PMCSR)153Chapter 5 Operational Characteristics1555.1 Absolute Maximum Ratings*1555.2 Operating Conditions**1555.3 Power Consumption1565.3.1 D0 - Normal Operation with Ethernet Traffic156Table 5.1 D0 - Normal Operation - Supply and Current (Typical)1565.3.2 D3 - Enabled for Wake Up Packet Detection157Table 5.2 D3 - Enabled for Wake Up Packet Detection - Supply and Current (Typical)1575.3.3 D3 - Enabled for Link Status Change Detection (Energy Detect)157Table 5.3 D3 - Enabled for Link Status Change Detection - Supply and Current (Typical)1575.3.4 D3 - PHY in General Power Down Mode158Table 5.4 D3 - PHY in General Power Down Mode - Supply and Current (Typical)1585.3.5 Maximum Power Consumption158Table 5.5 Maximum Power Consumption - Supply and Current (Maximum)1585.4 DC Specifications159Table 5.6 I/O Buffer Characteristics159Table 5.7 100BASE-TX Transceiver Characteristics160Table 5.8 10BASE-T Transceiver Characteristics1605.5 AC Specifications1615.5.1 Equivalent Test Load (Non-PCI Signals)161Figure 5.1 Output Equivalent Test Load1615.6 PCI Clock Timing162Figure 5.2 PCI Clock Timing162Table 5.9 PCI Clock Timing Values1625.7 PCI I/O Timing163Figure 5.3 PCI I/O Timing163Table 5.10 PCI I/O Timing Measurement Conditions163Table 5.11 PCI I/O Timing Values1645.8 EEPROM Timing165Figure 5.4 EEPROM Timing165Table 5.12 EEPROM Timing Values1655.9 Clock Circuit166Table 5.13 LAN9420/LAN9420i Crystal Specifications166Chapter 6 Package Outline1676.1 128-VTQFP Package167Figure 6.1 LAN9420/LAN9420i 128-VTQFP Package Definition167Table 6.1 LAN9420/LAN9420i 128-VTQFP Dimensions168Figure 6.2 LAN9420/LAN9420i 128-VTQFP Recommended PCB Land Pattern168Chapter 7 Revision History169Table 7.1 Customer Revision History169Size: 1.74 MBPages: 169Language: EnglishOpen manual
