User ManualTable of ContentsChapter 1 General Description61.1 Product Description6Chapter 2 Functional Block Diagram7Figure 2.1 USB3290 Block Diagram7Chapter 3 Pinout8Figure 3.1 USB3290 Pinout - Top View8Chapter 4 Interface Signal Definition9Table 4.1 System Interface Signals9Table 4.2 Data Interface Signals10Table 4.3 USB I/O Signals10Table 4.4 Biasing and Clock Oscillator Signals10Table 4.5 Power and Ground Signals11Chapter 5 Limiting Values12Table 5.1 Absolute Maximum Ratings12Table 5.2 Recommended Operating Conditions12Table 5.3 Recommended External Clock Conditions12Chapter 6 Electrical Characteristics13Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1)13Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2)13Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3)14Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4)15Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5)166.1 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers16Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver17Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver176.2 High-speed Signaling Eye Patterns18Figure 6.3 Eye Pattern Measurement Planes18Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition19Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition20Chapter 7 Functional Overview217.1 Modes of Operation217.2 System Clocking21Figure 7.1 FS CLK Relationship to Transmit Data and Control Signals21Figure 7.2 FS CLK Relationship to Receive Data and Control Signals227.3 Clock and Data Recovery Circuit227.4 TX Logic22Figure 7.3 Transmit Timing for a Data Packet227.5 RX Logic23Figure 7.4 Receive Timing for Data with Unstuffed Bits23Figure 7.5 Receive Timing for a Handshake Packet (no CRC)24Figure 7.6 Receive Timing for Setup Packet25Figure 7.7 Receive Timing for Data Packet (with CRC-16)257.6 USB 2.0 Transceiver267.6.1 High Speed and Full Speed Transceivers267.6.2 Termination Resistors26Table 7.1 DP/DM Termination vs. Signaling Mode267.6.3 Bias Generator277.7 Crystal Oscillator and PLL277.8 Internal Regulators and POR277.8.1 Internal Regulators277.8.2 Power On Reset (POR)277.8.3 Reset Pin27Chapter 8 Application Notes288.1 Linestate28Table 8.1 Linestate States288.2 OPMODES29Table 8.2 Operational Modes298.3 Test Mode Support29Table 8.3 USB 2.0 Test Modes298.4 SE0 Handling308.5 Reset Detection30Figure 8.1 Reset Timing Behavior (HS Mode)30Table 8.4 Reset Timing Values (HS Mode)308.6 Suspend Detection31Figure 8.2 Suspend Timing Behavior (HS Mode)31Table 8.5 Suspend Timing Values (HS Mode)318.7 HS Detection Handshake328.8 HS Detection Handshake - FS Downstream Facing Port32Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode)33Table 8.6 HS Detection Handshake Timing Values (FS Mode)338.9 HS Detection Handshake - HS Downstream Facing Port34Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram34Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode)35Table 8.7 Reset Timing Values358.10 HS Detection Handshake - Suspend Timing36Figure 8.6 HS Detection Handshake Timing Behavior from Suspend37Table 8.8 HS Detection Handshake Timing Values from Suspend378.11 Assertion of Resume38Figure 8.7 Resume Timing Behavior (HS Mode)38Table 8.9 Resume Timing Values (HS Mode)388.12 Detection of Resume398.13 HS Device Attach39Figure 8.8 Device Attach Behavior40Table 8.10 Attach and Reset Timing Values408.14 Application Diagram41Figure 8.9 USB3290 Application Diagram showing USB related signals41Figure 8.10 USB3290 Application Diagram showing power and miscellaneous signals42Chapter 9 Package Outline43Figure 9.1 USB3290-FH 40 Ball, VFBGA Package Outline & Parameters 4x4x0.9mm Body, Lead-Free RoHS Compliant43Figure 9.2 BGA, 4x4 Taping Dimensions and Part Orientation44Figure 9.3 Reel Dimensions for 12mm Carrier Tape45Figure 9.4 Tape Length and Part Quantity46Size: 859 KBPages: 46Language: EnglishOpen manual
User ManualTable of ContentsChapter 1 General Description61.1 Product Description6Chapter 2 Functional Block Diagram7Figure 2.1 USB3290 Block Diagram7Chapter 3 Pinout8Figure 3.1 USB3290 Pinout - Top View8Chapter 4 Interface Signal Definition9Table 4.1 System Interface Signals9Table 4.2 Data Interface Signals10Table 4.3 USB I/O Signals10Table 4.4 Biasing and Clock Oscillator Signals10Table 4.5 Power and Ground Signals11Chapter 5 Limiting Values12Table 5.1 Absolute Maximum Ratings12Table 5.2 Recommended Operating Conditions12Table 5.3 Recommended External Clock Conditions12Chapter 6 Electrical Characteristics13Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1)13Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2)13Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3)14Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4)15Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5)166.1 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers16Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver17Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver176.2 High-speed Signaling Eye Patterns18Figure 6.3 Eye Pattern Measurement Planes18Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition19Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition20Chapter 7 Functional Overview217.1 Modes of Operation217.2 System Clocking21Figure 7.1 FS CLK Relationship to Transmit Data and Control Signals21Figure 7.2 FS CLK Relationship to Receive Data and Control Signals227.3 Clock and Data Recovery Circuit227.4 TX Logic22Figure 7.3 Transmit Timing for a Data Packet227.5 RX Logic23Figure 7.4 Receive Timing for Data with Unstuffed Bits23Figure 7.5 Receive Timing for a Handshake Packet (no CRC)24Figure 7.6 Receive Timing for Setup Packet25Figure 7.7 Receive Timing for Data Packet (with CRC-16)257.6 USB 2.0 Transceiver267.6.1 High Speed and Full Speed Transceivers267.6.2 Termination Resistors26Table 7.1 DP/DM Termination vs. Signaling Mode267.6.3 Bias Generator277.7 Crystal Oscillator and PLL277.8 Internal Regulators and POR277.8.1 Internal Regulators277.8.2 Power On Reset (POR)277.8.3 Reset Pin27Chapter 8 Application Notes288.1 Linestate28Table 8.1 Linestate States288.2 OPMODES29Table 8.2 Operational Modes298.3 Test Mode Support29Table 8.3 USB 2.0 Test Modes298.4 SE0 Handling308.5 Reset Detection30Figure 8.1 Reset Timing Behavior (HS Mode)30Table 8.4 Reset Timing Values (HS Mode)308.6 Suspend Detection31Figure 8.2 Suspend Timing Behavior (HS Mode)31Table 8.5 Suspend Timing Values (HS Mode)318.7 HS Detection Handshake328.8 HS Detection Handshake - FS Downstream Facing Port32Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode)33Table 8.6 HS Detection Handshake Timing Values (FS Mode)338.9 HS Detection Handshake - HS Downstream Facing Port34Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram34Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode)35Table 8.7 Reset Timing Values358.10 HS Detection Handshake - Suspend Timing36Figure 8.6 HS Detection Handshake Timing Behavior from Suspend37Table 8.8 HS Detection Handshake Timing Values from Suspend378.11 Assertion of Resume38Figure 8.7 Resume Timing Behavior (HS Mode)38Table 8.9 Resume Timing Values (HS Mode)388.12 Detection of Resume398.13 HS Device Attach39Figure 8.8 Device Attach Behavior40Table 8.10 Attach and Reset Timing Values408.14 Application Diagram41Figure 8.9 USB3290 Application Diagram showing USB related signals41Figure 8.10 USB3290 Application Diagram showing power and miscellaneous signals42Chapter 9 Package Outline43Figure 9.1 USB3290-FH 40 Ball, VFBGA Package Outline & Parameters 4x4x0.9mm Body, Lead-Free RoHS Compliant43Figure 9.2 BGA, 4x4 Taping Dimensions and Part Orientation44Figure 9.3 Reel Dimensions for 12mm Carrier Tape45Figure 9.4 Tape Length and Part Quantity46Size: 859 KBPages: 46Language: EnglishOpen manual