Data Sheet (EVAL6460)Table of ContentsTable 1. Device summary11 General description101.1 Overview10Figure 1. Block diagram101.2 Pin connection11Figure 2. Pin connection111.3 Pin list12Table 2. Pins configuration122 L6460’s main features143 Electrical specifications163.1 Absolute maximum rating16Table 3. Absolute maximum ratings163.2 Operating ratings specifications16Table 4. IC operating ratings163.3 Electrical characteristics17Table 5. Electrical characteristics174 Internal supplies304.1 VSupplyInt regulator30Figure 3. VSupplyInt pin304.2 Charge pump regulator31Figure 4. Charge pump block diagram314.3 V3v3 regulator315 Supervisory system325.1 Power on reset (POR) circuit325.2 nRESET generation circuit32Table 6. Stretch time selection33Figure 5. nReset generation circuit345.3 Thermal shut down generation circuit356 Watchdog circuit36Figure 6. Watchdog circuit block diagram36Table 7. Watchdog timeout specifications377 Internal clock oscillator388 Start-up configurations39Table 8. Possible start-up pins state symbol398.1 Operation modes39Table 9. Start-up correspondence408.2 Basic device mode408.3 Slave device mode418.4 Master device mode418.5 Single device mode418.6 Sub-configurations for slave, master or single device modes418.6.1 Bridge mode418.6.2 Primary regulator mode (KP)428.6.3 Regulators mode428.6.4 Simple regulator mode (KT)428.6.5 Bridge + VEXT mode428.6.6 Secondary regulators mode439 Power sequencing4410 Power saving modes4510.1 Standby mode45Figure 7. Standby mode function description4510.2 Hibernate mode4610.3 Low power mode4610.4 nAWAKE pin46Figure 8. nAWAKE function block diagram4711 Linear main regulator48Figure 9. Linear main regulator48Figure 10. Linear main regulator with external bipolar for high current4912 Main switching regulator5012.1 Pulse skipping operation50Figure 11. Main switching regulator functional blocks51Table 10. Main switching regulator PWM specification51Table 11. Main switching regulator current limit5113 Switching regulator controller52Figure 12. Switching regulator controller functional blocks5313.1 Pulse skipping operation53Table 12. Switching regulator controller PWM specification5313.2 Output equivalent circuit54Figure 13. Switching regulator controller output driving: equivalent circuit5413.3 Switching regulator controller application considerations54Table 13. Switching regulator controller application: feedback reference5414 Power bridges56Figure 14. H Bridge block diagram56Table 14. PWM selection truth table for bridge 1 or 257Table 15. PWM selection truth table for bridge 3 or 457Figure 15. Bridge 1 and 2 PWM selection5814.1 Possible configurations59Table 16. Bridge selection59Table 17. Bridge 3 and 4 configuration5914.1.1 Full bridge60Table 18. Full bridge truth table6014.1.2 Parallel configuration (super bridge)61Figure 16. Super bridge configuration6114.1.3 Half bridge configuration61Figure 17. Half bridge configuration62Table 19. Half bridge truth table6214.1.4 Switch configuration63Table 20. Switch truth table6314.1.5 Bipolar stepper configuration63Figure 18. Bipolar stepper configuration65Table 21. Sequencer driver66Table 22. Stepper driving mode66Table 23. Stepper sequencer direction67Table 24. DAC68Table 25. Internal sequencer69Table 26. Stepper off time71Table 27. Stepper fast decay7314.1.6 Synchronous buck regulator configuration (Bridge 3)73Figure 19. Regulator block diagram74Table 28. PWM specification7514.1.7 Regulation loop75Figure 20. Internal comparator functional block diagram7514.1.8 Battery charger or switching regulator (Bridge 4)76Figure 21. Battery charger control loop block diagram76Figure 22. Li-ion battery charge profile77Figure 23. Simple buck regulator78Table 29. Battery charger regulator controller PWM specification7915 AD converter80Figure 24. A2D block diagram81Table 30. ADC truth table81Table 31. Channel addresses82Table 32. ADC sample times when working as a 8-bit ADC83Table 33. ADC sample time when working as a 9-bit ADC8315.1 Voltage divider specifications84Table 34. Voltage divider specification8416 Current DAC circuit85Figure 25. Current DAC block diagram85Table 35. Current DAC truth table8617 Operational amplifiers87Figure 26. Configurable 3.3 V operational amplifiers8718 Low voltage power switches89Figure 27. Low power switch block diagram8919 General purpose PWM9019.1 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2)9019.2 Programmable PWM generator (GpPwm)9020 Interrupt controller91Figure 28. Interrupt controller diagram91Table 36. Interrupt controller event9121 Digital comparator93Figure 29. Digital comparator block diagram94Table 37. Comparison type truth table94Table 38. DataX selection truth table9422 GPIO pins95Table 39. GPIO functions description95Table 40. Abbreviations9722.1 GPIO[0]99Table 41. GPIO[0] truth table99Figure 30. GPIO[0] block diagram10022.2 GPIO[1]101Table 42. GPIO[1] truth table101Figure 31. GPIO[1] block diagram10222.3 GPIO[2]103Table 43. GPIO[2] truth table103Figure 32. GPIO[2] block diagram10422.4 GPIO[3]105Table 44. GPIO[3] truth table105Figure 33. GPIO[3] block diagram10622.5 GPIO[4]107Table 45. GPIO[4] truth table107Figure 34. GPIO[4] block diagram10822.6 GPIO[5]109Table 46. GPIO[5] truth table109Figure 35. GPIO[5] block diagram11022.7 GPIO[6]111Table 47. GPIO[6] truth table111Figure 36. GPIO[6] block diagram11222.8 GPIO[7]113Table 48. GPIO[7] truth table113Figure 37. GPIO[7] block diagram11422.9 GPIO[8]115Table 49. GPIO[8] truth table115Figure 38. GPIO[8] block diagram11622.10 GPIO[9]117Table 50. GPIO[9] truth table117Figure 39. GPIO[9] block diagram11822.11 GPIO[10]119Table 51. GPIO[10] truth table119Figure 40. GPIO[10] block diagram12022.12 GPIO[11]121Table 52. GPIO[11] truth table121Figure 41. GPIO[11] block diagram12222.13 GPIO[12]123Table 53. GPIO[12] truth table123Figure 42. GPIO[12] block diagram12422.14 GPIO[13]125Table 54. GPIO[13] truth table125Figure 43. GPIO[13] block diagram12622.15 GPIO[14]127Table 55. GPIO[14] truth table127Figure 44. GPIO[14] block diagram12823 Serial interface12923.1 Read transaction129Figure 45. SPI read transaction13023.2 Write transaction130Figure 46. SPI write transaction130Figure 47. SPI input timing diagram131Figure 48. SPI output timing diagram13124 Registers list132Table 56. Register address map13225 Schematic examples135Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies135Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies13626 Package mechanical data137Figure 51. TQFP64 mechanical data an package dimensions13727 Revision history138Table 57. Document revision history138Size: 3.73 MBPages: 139Language: EnglishOpen manual