Casio G486VPB Manual De Usuario
PCI/ISA System Board
14
Cache Configuration
The G486VPB system board can be configured to three
different cache sizes: 128KB (default size), 256KB, and
512KB. Regardless of the amount of cache memory
installed, one 8Kx8 or 32Kx8 is needed for tag RAM to
store the cacheable addresses. The locations of the
SRAM sockets and Jumpers JP10-JP14 on the system
board are shown below.
different cache sizes: 128KB (default size), 256KB, and
512KB. Regardless of the amount of cache memory
installed, one 8Kx8 or 32Kx8 is needed for tag RAM to
store the cacheable addresses. The locations of the
SRAM sockets and Jumpers JP10-JP14 on the system
board are shown below.
Locations of the SRAM Sockets and Jumpers JP10-JP14
on the G486VPB System Board