Siemens ERTEC200 Manual De Usuario
2.2 Description of ARM946E-S
The ARM946E-S processor system is a member of the ARM9 Thumb family. It has a processor core with Harvard
architecture. Compared to the standard ARM9 family, the ARM946E-S has an enhanced V5TE architecture permitting
faster switching between ARM and Thumb code segments and an enhanced multiplier structure. In addition, the
processor has an integrated JTAG interface.
architecture. Compared to the standard ARM9 family, the ARM946E-S has an enhanced V5TE architecture permitting
faster switching between ARM and Thumb code segments and an enhanced multiplier structure. In addition, the
processor has an integrated JTAG interface.
2.3 Operating Frequency of ARM946E-S
The processor can be operated at 50 MHz, 100 MHz, or 150 MHz. The operating frequency is set during the reset phase
via the configuration pins CONFIG[4] and CONFIG[3]. Communication with the components of the ERTEC 200 takes
place via the AHB bus at a frequency of 50 MHz.
via the configuration pins CONFIG[4] and CONFIG[3]. Communication with the components of the ERTEC 200 takes
place via the AHB bus at a frequency of 50 MHz.
2.4 Cache Structure of ARM946E-S
The following caches are integrated in the ARM946E-S.
•
8 Kbytes of instruction cache with lock function
•
4 Kbytes of data cache with lock function
Both caches are “Four-Way Set Associative” caches with 1-Kbyte segments. Each segment consists of 32 lines with 32
bytes (8 x 4 bytes). The D-cache has “write buffers" with write-back function.
The lock function enables the user to lock (LOCK) the contents of the cache segments. This function enables the
command set for fast routines to be maintained permanently in the instruction cache. This mechanism can only be
applied at the segment level with the ARM946E-S.
Both caches are locked after a reset. These caches can only be enabled if the Memory Protection Unit is also enabled.
The I-cache can be enabled by setting Bit 12 of the CP15 control register.
The D-cache can be enabled by setting Bit 2 of the CP15 control register.
Access to this area is blocked if the cache is not enabled.
For additional information about Caching refer to Document /1/ Section 3.
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document.
command set for fast routines to be maintained permanently in the instruction cache. This mechanism can only be
applied at the segment level with the ARM946E-S.
Both caches are locked after a reset. These caches can only be enabled if the Memory Protection Unit is also enabled.
The I-cache can be enabled by setting Bit 12 of the CP15 control register.
The D-cache can be enabled by setting Bit 2 of the CP15 control register.
Access to this area is blocked if the cache is not enabled.
For additional information about Caching refer to Document /1/ Section 3.
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document.
2.5 Tightly Coupled Memory (TCM)
A 4-Kbyte data-tightly coupled memory (D-TCM) is implemented in the ARM946E-S processor of the ERTEC 200. The
memory is locked after a reset. The D-TCM can be placed in the address area of the ARM946E-S as desired and must
be used together with a region of the memory protection unit. Data from high-speed routines such as isochronous control
can be placed in the D-TCM.
The D-TCM can be enabled by setting Bit 16 of the CP15 control register.
In addition, the address area of the D-TCM must be set in the Tightly-Coupled Memory register.
For more information about the D-TCM refer to document /1/ Section 5.
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document.
memory is locked after a reset. The D-TCM can be placed in the address area of the ARM946E-S as desired and must
be used together with a region of the memory protection unit. Data from high-speed routines such as isochronous control
can be placed in the D-TCM.
The D-TCM can be enabled by setting Bit 16 of the CP15 control register.
In addition, the address area of the D-TCM must be set in the Tightly-Coupled Memory register.
For more information about the D-TCM refer to document /1/ Section 5.
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document.
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ERTEC 200 Manual
Technical data subject to change Version 1.1.0