Intel 253668-032US Manual De Usuario
Vol. 3 6-35
INTERRUPT AND EXCEPTION HANDLING
processor and earlier IA-32 processors, this exception is not generated as the result
of prefetching and preliminary decoding of an invalid instruction. (See Section 6.5,
“Exception Classifications,” for general rules for taking of interrupts and exceptions.)
The opcodes D6 and F1 are undefined opcodes reserved by the Intel 64 and IA-32
architectures. These opcodes, even though undefined, do not generate an invalid
opcode exception.
The UD2 instruction is guaranteed to generate an invalid opcode exception.
of prefetching and preliminary decoding of an invalid instruction. (See Section 6.5,
“Exception Classifications,” for general rules for taking of interrupts and exceptions.)
The opcodes D6 and F1 are undefined opcodes reserved by the Intel 64 and IA-32
architectures. These opcodes, even though undefined, do not generate an invalid
opcode exception.
The UD2 instruction is guaranteed to generate an invalid opcode exception.
Exception Error Code
None.
Saved Instruction Pointer
The saved contents of CS and EIP registers point to the instruction that generated the
exception.
exception.
Program State Change
A program-state change does not accompany an invalid-opcode fault, because the
invalid instruction is not executed.
invalid instruction is not executed.