BEI Electronics LLC 7EPTX-AM5E Manual De Usuario

1-32

1-153.

The mono/stereo mode decoder circuit consists of:  1) latches U44B, U51A, and U51B and

2) mono/stereo decoder logic U41D, U43B, U43C, U52C, and U52D.  Latches U51A and

U51B latch the two bit binary code and produce complementary outputs for application to

the mono/stereo decoder logic.  Latch U44B operates as a clock for U51A/U51B.  The

mono/stereo decoder logic decodes the binary code and outputs a HIGH to:  1) transistors

Q5, Q9, and Q14 and 2) equalization select integrated circuits U23 and U28.  Transistor

Q14 will respond by generating a LOW internal stereo status signal.  Transistor Q5 will

output a LOW to bias stereo indicator DS3 to on.  Transistor Q9 will respond by 

generating a LOW remote stereo status signal.

1-154.

Selection and indication of the mono left, mono right, and mono L+R modes of operation

are performed in an identical manner.  When the mono left or mono right mode is 

selected, a HIGH will be routed to NAND gate U43D.  The output of U43D will go HIGH.

The HIGH is inverted at U55D to produce a LOW mono single channel signal for

application to the exciter circuit board. When the mono left, mono right, or mono L+R 

mode is selected a HIGH is applied to transistor Q13.  Q13 will respond by generating a

LOW remote mono status signal.

1-155.

EQUALIZATION SELECTION.  

Equalization circuit selection is determined by the antenna

connected to the transmitter.  Antenna A selects equalization circuit 1.  Antenna B selects

equalization circuit 2.  Antenna C can be programmed to select equalization circuit 1 or

equalization circuit 2.

1-156.

Antenna A, B, and C status signals are applied to AND gates U41A and U41B.

Programmable jumper P6 selects equalization circuit 1 or equalization circuit 2 for

antenna C operations.

1-157.

The circuit selects equalization circuit 1 or 2 when a status signal is applied to

U41A/U41B.  For example, a LOW is applied to U41B when antenna A is selected.  U41B

will output a LOW to NAND gate U43A.  Programmable jumper P7 programs the

equalization selection circuit for momentary or continuous signals.  With P7 programmed

for momentary signals, U43A will output a HIGH to AND gate U41C.  With a HIGH from

U41A, U41C will output a HIGH to latch U44A.  U44A will output a HIGH to:

1) integrated circuits U23 and U28 to select equalization circuit 1 and 2) transistor Q4.  

Q4 will go LOW to bias equalization 1 indicator DS1 on.

1-158.

PILOT SIGNAL.  

A 25 Hz square-wave signal from the exciter circuit board is applied

through potentiometer R132 to a band-pass filter consisting of integrated circuits U30A

and U30B.  Potentiometer R132 is designed to provide pilot level control.  The band-pass

filter converts the square-wave signal to a sine-wave signal.

1-159.

The output of the band-pass filter is applied through switch S1 to:  1) integrated circuit

U23 and 2) inverter U31A.  U31A inverts the signal for application to integrated circuit

U28.  Switch S1 is provided to disable the pilot signal.

1-160.

POWER SUPPLY FILTER NETWORK.  

The stereo circuit board operates from 

±

15 volt 

power supplies.  Each supply is equipped with a filter network.  The +15 volt supply filter

consists of inductor L1 and capacitor C92.  The output of the filter is applied to the stereo

circuit board components.  The -15 volt supply filter consists of inductor L2 and capacitor

C94.  The output of the filter is applied to the stereo circuit board components.

1-161.

ECU POWER SUPPLY ASSEMBLY.

1-162.

The ECU assembly is equipped with a modular 40W switching power supply assembly.

The supply provides regulated +5V, +15V, and -15V operating potentials for the ECU

circuit boards.