Intel i7-3920XM Extreme AW8063801009607 Manual De Usuario
Los códigos de productos
AW8063801009607
Processor Configuration Registers
98
Datasheet, Volume 2
2.6.16
MLIMIT—Memory Limit Address Register
This register controls the processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper
12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode, address bits A[19:0] are
assumed to be FFFFFh. Thus, the top of the defined memory address range will be at
the top of a 1 MB aligned memory block.
12 address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode, address bits A[19:0] are
assumed to be FFFFFh. Thus, the top of the defined memory address range will be at
the top of a 1 MB aligned memory block.
Note:
Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express-G address ranges (typically where control/status memory-
mapped I/O data structures of the graphics controller will reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved
processor-PCI Express memory access performance.
Note:
Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges;
that is, prevent overlap with each other and/or with the ranges covered with the main
memory. There is no provision in the processor hardware to enforce prevention of
overlap and operations of the system in the case of overlap are not ensured.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
22–23h
Reset Value:
0000h
Access:
RW
Size:
16 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
15:4
RW
000h
Uncore
Memory Address Limit (MLIMIT)
This field corresponds to A[31:20] of the upper limit of the
This field corresponds to A[31:20] of the upper limit of the
address range passed to PCI Express-G.
3:0
RO
0h
Reserved (RSVD)