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AT91SAM9N12-EK
Tightly-Coupled Memory Interface
5-20
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
5.5
TCM interface examples
This section contains the following examples:
•
•
•
Note
Most of the examples in this section are for the DTCM interface. These are also
applicable to the ITCM interface.
applicable to the ITCM interface.
The additional logic required for implementing the examples in this section is the
responsibility of the implementer.
responsibility of the implementer.
5.5.1
Zero-wait-state RAM example
Figure 5-12 shows the simplest RAM interface where the RAM block is constructed
from a single word-wide RAM that has byte write control. The TCM interface can
connect directly to the RAM block. This is a zero-wait-state memory so DRWAIT is
tied LOW.
from a single word-wide RAM that has byte write control. The TCM interface can
connect directly to the RAM block. This is a zero-wait-state memory so DRWAIT is
tied LOW.
Figure 5-12 Zero wait state RAM example
5.5.2
Producing byte writable memory using word writable RAM
If byte-write RAM is not available, four banks of byte-wide RAM must be used as
shown in Figure 5-13 on page 5-21.
shown in Figure 5-13 on page 5-21.
DRSIZE[3:0]
DRIDLE
DRADDR[17:0]
DRWD[31:0]
DRWBL[3:0]
DRCS
DRRD[31:0]
DRSEQ
DRWAIT
ARM926EJ-S
RAM 32KB
CLK
A[14:0]
CLK
DIN[31:0]
BW[3:0]
CS
CS
DOUT[31:0]
[14:0]
b0110
DRnRW
nRW