Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos

121

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

RSTC_MR

0xFFFFFE08

Read-write

This field defines the external reset length. The external reset is asserted during a time of 2

(ERSTL+1)

 Slow Clock cycles. This 

allows the assertion duration to be programmed between 60 µs and 2 seconds.

31

30

29

28

27

26

25

24

KEY

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

ERSTL

7

6

5

4

3

2

1

0

–

–

– 

–

–

–

–

0xA5

PASSWD

Writing any other value in this field aborts the write operation.

Always reads as 0.