Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

This arbitration algorithm is the first and only applied between masters from distinct priority pools. It is also used inside
priority pools other than the highest and lowest ones (intermediate priority pools).

It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed
priority defined by the user in the MxPR field for each master inside the MATRIX_PRAS and MATRIX_PRBS Priority
Registers. If two or more master requests are active at the same time, the master with the highest priority number MxPR
is serviced first.

Inside intermediate priority pools, if two or more master requests with the same priority are active at the same time, the
master with the highest number is serviced first.

This algorithm is only used inside the highest and lowest priority pools. It allows the Bus Matrix arbiters to dispatch the
requests from different masters to the same slave in a fair way. If two or more master requests are active at the same
time inside the priority pool, they are serviced in a round-robin increasing master number order.

To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address
offset 0x000 to 0x1FC can be write protected by setting the WPEN bit in the MATRIX Write Protect Mode Register
(MATRIX_WPMR).

If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the
WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.

The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate
access key WPKEY.