Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos

682

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The PWM macrocell controls several channels independently. Each channel controls one square output waveform.
Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user
interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator
provides several clocks resulting from the division of the PWM macrocell master clock.

All PWM macrocell accesses are made through APB mapped registers. 

Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system
in order to

 

prevent

 

an unexpected output waveform while modifying the period or the duty-cycle.



4 Channels



One 32-bit Counter Per Channel



Common Clock Generator Providing Thirteen Different Clocks 



A Modulo n Counter Providing Eleven Clocks



Two Independent Linear Dividers Working on Modulo n Counter Outputs



Independent Channels



Independent Enable Disable Command for Each Channel



Independent Clock Selection for Each Channel



Independent Period and Duty Cycle for Each Channel



Double Buffering of Period or Duty Cycle for Each Channel



Programmable Selection of The Output Waveform Polarity for Each Channel



Programmable Center or Left Aligned Output Waveform for Each Channel Block Diagram