Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos
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AT91SAM9N12-EK
704
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
38.7.13 PWM Channel Update Register
Name:
PWM_CUPD[0..3]
Address:
0xF8034210 [0], 0xF8034230 [1], 0xF8034250 [2], 0xF8034270 [3]
Access:
Write-only
CUPD: Channel Update Register
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the
waveform period or duty-cycle.
waveform period or duty-cycle.
Only the first 32 bits (internal channel counter size) are significant.
When CPD field of PWM_CMRx register = 0, the duty-cycle (CDTY of PWM_CDTYx register) is updated with the CUPD value at
the beginning of the next period.
the beginning of the next period.
When CPD field of PWM_CMRx register = 1, the period (CPRD of PWM_CPRDx register) is updated with the CUPD value at the
beginning of the next period.
beginning of the next period.
31
30
29
28
27
26
25
24
CUPD
23
22
21
20
19
18
17
16
CUPD
15
14
13
12
11
10
9
8
CUPD
7
6
5
4
3
2
1
0
CUPD