Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos
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AT91SAM9N12-EK
936
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
43.9.5 SSC Transmit Clock Mode Register
Name:
SSC_TCMR
Address:
0xF0010018
Access:
Read-write
This register can only be written if the WPEN bit is cleared in
.
• CKS: Transmit Clock Selection
• CKO: Transmit Clock Output Mode Selection
• CKI: Transmit Clock Inversion
0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input
is sampled on Transmit clock rising edge.
is sampled on Transmit clock rising edge.
1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input
is sampled on Transmit clock falling edge.
is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
• CKG: Transmit Clock Gating Selection
31
30
29
28
27
26
25
24
PERIOD
23
22
21
20
19
18
17
16
STTDLY
15
14
13
12
11
10
9
8
–
–
–
–
START
7
6
5
4
3
2
1
0
CKG
CKI
CKO
CKS
Value
Name
Description
0
MCK
Divided Clock
1
RK
RK Clock signal
2
TK
TK pin
Value
Name
Description
0
NONE
None, TK pin is an input
1
CONTINUOUS
Continuous Transmit Clock, TK pin is an output
2
TRANSFER
Transmit Clock only during data transfers, TK pin is an output
Value Name
Description
0
CONTINUOUS
None
1
EN_TF_LOW
Transmit Clock enabled only if TF Low
2
EN_TF_HIGH
Transmit Clock enabled only if TF High