STMicroelectronics Discovery kit for STM32L151/152 line - with STM32L152RC MCU STM32L152C-DISCO STM32L152C-DISCO Hoja De Datos

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The STM32L15xxC devices have the following features:


32 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait 
states. With the enhanced bus matrix, operating the RAM does not lead to any 
performance penalty during accesses to the system bus (AHB and APB buses).



The non-volatile memory is divided into three arrays:
–

256 Kbytes of embedded Flash program memory

–

8 Kbytes of data EEPROM

–

Options bytes

The options bytes are used to write-protect or read-out protect the memory (with 4 KB 
granularity) and/or readout-protect the whole memory with the following options:
–

Level 0: no readout protection

–

Level 1: memory readout protection, the Flash memory cannot be read from or 
written to if either debug features are connected or boot in RAM is selected

–

Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial 
wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, 
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports 
circular buffer management, avoiding the generation of interrupts when the controller 
reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger 
support for each channel. Configuration is done by software and transfer sizes between 
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

2

C, USART, general-purpose timers, 

DAC and ADC.