Intel E3815 FH8065301567411 Hoja De Datos
Los códigos de productos
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1995
17.8.39
Port-Serial ATA Active (PxSACT1)—Offset 1B4h
Access Method
Default: 00000000h
17.8.40
Port-Commands Issued (PxCI1)—Offset 1B8h
Access Method
Default: 00000000h
17.8.41
Port-Device Sleep (PxDEVSLP1)—Offset 1C4h
Access Method
Default: 1E022852h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxSACT1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DS
Bit
Range
Default &
Access
Description
31:0
00000000h
RW/1S
Device Status (DS):
System software sets this bit for native command queuing
commands prior to setting the PxCI.CI bit in the same command slot entry. This field is
cleared via the Set Device Bits FIS.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxCI1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CI
Bit
Range
Default &
Access
Description
31:0
00000000h
RW
Commands Issued (CI):
This field is set by software to indicate to the HBA that a
command has been built in system memory for a command slot and may be sent to the
device. When the HBA receives a FIS which clears the BSY, ERR, and DRQ bits for the
command, it clears the corresponding bit in this register for that command slot. Bits in
this field shall only be set to 1 by software when PxCMD.ST is set to 1.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxDEVSLP1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h