Intel E3815 FH8065301567411 Hoja De Datos

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3825

If the master is receiving data as shown in 

, the master responds to the 

Slave-Transmitter with an acknowledge pulse after a byte of data has been received, 
except for the last byte. This is the way the Master-Receiver notifies the Slave-
Transmitter that this is the last byte. The Slave-Transmitter relinquishes the data line 
after detecting the No Acknowledge (NACK) so that the master can issue a STOP 
condition.

When a master does not want to relinquish the bus with a STOP condition, the master 
can issue a RESTART condition. This is identical to a START condition except it occurs 
after the ACK pulse. The master can then communicate with the same slave or a 
different slave.

The START BYTE Transfer protocol is set up for systems that do not have an on-board 
dedicated I

2

C hardware module. When the I

2

C controller is a master, it supports the 

generation of START BYTE transfers at the beginning of every transfer in case a slave 
device requires it. This protocol consists of 7 ‘0’s being transmitted followed by a 1, as 
illustrated in 

. This allows the processor that is polling the bus to under-

sample the address phase until 0s are detected. Once the microcontroller detects a 0, it 
switches from the under sampling rate to the correct rate of the master.

S

DATA

DATA

R/W

Slave Address

A

P

A

S

Sr

Slave Address

Second Byte

R/W

Slave Address

First 7 bits

A

P

A

For 10-bit Address

0' (write)

From Master to Slave

From Slave to Master

A = Acknowledge (Data low)

A = No Acknowledge (Data high)

S = START Condition

P = STOP Condition 

‘11110xxx’

‘1’ (read)

‘11110xxx’

Slave Address

First 7 bits

R/W

A

‘1’ (read)

DATA

A

A

R = RESTART Condition