Manual De UsuarioTabla de contenidosCortex-R4 and Cortex-R4F Technical Reference Manual1Contents3List of Tables7List of Figures13Preface16About this book17Product revision status17Intended audience17Using this book17Conventions18Further reading20Feedback21Feedback on this product21Feedback on this book21Introduction221.1 About the processor231.2 About the architecture241.3 Components of the processor251.3.1 Data Processing Unit261.3.2 Load/store unit261.3.3 Prefetch unit261.3.4 L1 memory system261.3.5 L2 AXI interfaces281.3.6 Debug291.3.7 System control coprocessor301.3.8 Interrupt handling301.4 External interfaces of the processor321.4.1 APB Debug interface321.4.2 ETM interface321.4.3 Test interface321.5 Power management331.6 Configurable options341.7 Execution pipeline stages381.8 Redundant core comparison401.9 Test features411.10 Product documentation, design flow, and architecture421.10.1 Documentation421.10.2 Design flow421.10.3 Architectural information431.11 Product revision information451.11.1 Processor identification451.11.2 Architectural information46Programmer’s Model472.1 About the programmer’s model482.2 Instruction set states492.2.1 Switching state492.2.2 Interworking ARM and Thumb state492.3 Operating modes502.4 Data types512.5 Memory formats522.5.1 Byte-invariant big-endian format522.5.2 Little-endian format522.6 Registers532.6.1 The register set532.7 Program status registers562.7.1 The N, Z, C, and V bits562.7.2 The Q bit572.7.3 The IT bits572.7.4 The J bit582.7.5 The DNM bits582.7.6 The GE bits582.7.7 The E bit592.7.8 The A bit592.7.9 The I and F bits592.7.10 The T bit592.7.11 The M bits602.7.12 Modification of PSR bits by MSR instructions602.8 Exceptions622.8.1 Exception entry and exit summary622.8.2 Reset642.8.3 Interrupts642.8.4 Aborts682.8.5 Supervisor call instruction702.8.6 Undefined instruction712.8.7 Breakpoint instruction712.8.8 Exception vectors722.9 Acceleration of execution environments732.10 Unaligned and mixed-endian data access support742.11 Big-endian instruction support75Processor Initialization, Resets, and Clocking763.1 Initialization773.1.1 MPU773.1.2 CRS773.1.3 FPU773.1.4 Caches783.1.5 TCM783.2 Resets813.3 Reset modes823.3.1 Power-on reset823.3.2 Processor reset833.3.3 Normal operation833.3.4 Halt operation833.4 Clocking843.4.1 AXI interface clocking843.4.2 Clock gating84System Control Coprocessor854.1 About the system control coprocessor864.1.1 System control coprocessor functional groups864.1.2 System control and configuration884.1.3 MPU control and configuration894.1.4 Cache control and configuration894.1.5 TCM control and configuration904.1.6 System performance monitor904.1.7 System validation914.2 System control coprocessor registers934.2.1 Register allocation934.2.2 c0, Main ID Register984.2.3 c0, Cache Type Register994.2.4 c0, TCM Type Register1004.2.5 c0, MPU Type Register1014.2.6 c0, Multiprocessor ID Register1024.2.7 The Processor Feature Registers1024.2.8 c0, Debug Feature Register 01044.2.9 c0, Auxiliary Feature Register 01054.2.10 Memory Model Feature Registers1054.2.11 Instruction Set Attributes Registers1104.2.12 c0, Current Cache Size Identification Register1164.2.13 c0, Current Cache Level ID Register1184.2.14 c0, Cache Size Selection Register1194.2.15 c1, System Control Register1194.2.16 Auxiliary Control Registers1224.2.17 c1, Coprocessor Access Register1284.2.18 Fault Status and Address Registers1294.2.19 c6, MPU memory region programming registers1334.2.20 Cache operations1384.2.21 c9, BTCM Region Register1414.2.22 c9, ATCM Region Register1424.2.23 c9, TCM Selection Register1434.2.24 c11, Slave Port Control Register1434.2.25 c13, FCSE PID Register1444.2.26 c13, Context ID Register1444.2.27 c13, Thread and Process ID Registers1454.2.28 Validation Registers1464.2.29 Correctable Fault Location Register1544.2.30 Build Options Registers156Prefetch Unit1605.1 About the prefetch unit1615.2 Branch prediction1625.2.1 Disabling program flow prediction1625.2.2 Branch predictor1635.2.3 Incorrect predictions and correction1635.3 Return stack164Events and Performance Monitor1656.1 About the events1666.2 About the PMU1706.3 Performance monitoring registers1716.3.1 c9, Performance Monitor Control Register1716.3.2 c9, Count Enable Set Register1726.3.3 c9, Count Enable Clear Register1736.3.4 c9, Overflow Flag Status Register1746.3.5 c9, Software Increment Register1756.3.6 c9, Performance Counter Selection Register1766.3.7 c9, Cycle Count Register1776.3.8 c9, Event Selection Register1776.3.9 c9, Performance Monitor Count Registers1796.3.10 c9, User Enable Register1796.3.11 c9, Interrupt Enable Set Register1806.3.12 c9, Interrupt Enable Clear Register1816.4 Event bus interface1836.4.1 Use of the event bus and counters183Memory Protection Unit1847.1 About the MPU1857.1.1 Memory regions1867.1.2 Overlapping regions1877.1.3 Background regions1897.1.4 TCM regions1897.2 Memory types1907.2.1 Using memory types1907.3 Region attributes1927.3.1 Cacheable memory policies1937.4 MPU interaction with memory system1947.5 MPU faults1957.5.1 Background fault1957.5.2 Permission fault1957.5.3 Alignment fault1957.6 MPU software-accessible registers196Level One Memory System1978.1 About the L1 memory system1988.2 About the error detection and correction schemes2008.2.1 Parity2008.2.2 Error checking and correction2018.2.3 Read-Modify-Write2018.2.4 Hard errors2018.2.5 Error correction2028.3 Fault handling2038.3.1 Faults2038.3.2 Fault status information2058.3.3 Correctable Fault Location Register2068.3.4 Usage models2068.4 About the TCMs2098.4.1 TCM attributes and permissions2098.4.2 ATCM and BTCM configuration2108.4.3 TCM internal error detection and correction2108.4.4 TCM arbitration2118.4.5 TCM initialization2128.4.6 TCM port protocol2128.4.7 External TCM errors2128.4.8 AXI slave interfaces for TCMs2138.5 About the caches2148.5.1 Store buffer2148.5.2 Cache maintenance operations2158.5.3 Cache error detection and correction2168.5.4 Cache RAM organization2228.5.5 Cache interaction with memory system2278.6 Internal exclusive monitor2308.7 Memory types and L1 memory system behavior2318.8 Error detection events2328.8.1 TCM error events2328.8.2 Instruction-cache error events2328.8.3 Data-cache error events2328.8.4 Events and the CFLR232Level Two Interface2349.1 About the L2 interface2359.2 AXI master interface2369.2.1 Identifiers for AXI bus accesses2379.2.2 Write response2379.2.3 Linefill buffers and the AXI master interface2379.2.4 Eviction buffer2389.2.5 Memory attributes2389.3 AXI master interface transfers2409.3.1 Restrictions on AXI transfers2419.3.2 Strongly Ordered and Device transactions2419.3.3 Linefills2469.3.4 Cache line write-back (eviction)2469.3.5 Non-cacheable reads2469.3.6 Non-cacheable or write-through writes2489.3.7 AXI transaction splitting2499.3.8 Normal write merging2509.4 AXI slave interface2539.4.1 AXI slave interface for cache RAMs2539.4.2 TCM parity and ECC support2549.4.3 External TCM errors2549.4.4 Cache parity and ECC support2549.4.5 AXI slave control2549.4.6 AXI slave characteristics2559.5 Enabling or disabling AXI slave accesses2569.6 Accessing RAMs using the AXI slave interface2579.6.1 TCM RAM access2589.6.2 Cache RAM access259Power Control26610.1 About power control26710.2 Power management26810.2.1 Run mode26810.2.2 Standby mode26810.2.3 Dormant mode26810.2.4 Shutdown mode26810.2.5 Communication to the Power Management Controller269Debug27011.1 Debug systems27111.1.1 Debug host27111.1.2 Protocol converter27111.1.3 Debug target27111.2 About the debug unit27211.2.1 Halting debug-mode debugging27211.2.2 Monitor debug-mode debugging27211.2.3 Programming the debug unit27211.3 Debug register interface27411.3.1 Coprocessor registers27411.3.2 CP14 access permissions27411.3.3 Coprocessor registers summary27411.3.4 Memory-mapped registers27511.3.5 Memory addresses for breakpoints and watchpoints27611.3.6 Power domains27711.3.7 Effects of resets on debug registers27711.3.8 APB port access permissions27711.4 Debug register descriptions27911.4.1 Accessing debug registers27911.4.2 CP14 c0, Debug ID Register27911.4.3 CP14 c0, Debug ROM Address Register28111.4.4 CP14 c0, Debug Self Address Offset Register28111.4.5 CP14 c1, Debug Status and Control Register28311.4.6 Data Transfer Register28711.4.7 Watchpoint Fault Address Register28811.4.8 Vector Catch Register28811.4.9 Debug State Cache Control Register29011.4.10 Instruction Transfer Register29011.4.11 Debug Run Control Register29111.4.12 Breakpoint Value Registers29211.4.13 Breakpoint Control Registers29211.4.14 Watchpoint Value Registers29511.4.15 Watchpoint Control Registers29511.4.16 Operating System Lock Status Register29711.4.17 Authentication Status Register29811.4.18 Device Power-down and Reset Control Register29911.4.19 Device Power-down and Reset Status Register29911.5 Management registers30111.5.1 Processor ID Registers30111.5.2 Claim Registers30211.5.3 Lock Access Register30311.5.4 Lock Status Register30311.5.5 Device Type Register30411.5.6 Debug Identification Registers30411.6 Debug events30811.6.1 Software debug event30811.6.2 Halting debug event30911.6.3 Behavior of the processor on debug events30911.6.4 Debug event priority30911.6.5 Watchpoint debug events30911.7 Debug exception31011.7.1 Effect of debug exceptions on CP15 registers and WFAR31111.7.2 Avoiding unrecoverable states31211.8 Debug state31311.8.1 Entering debug state31311.8.2 Behavior of the PC and CPSR in debug state31411.8.3 Executing instructions in debug state31511.8.4 Writing to the CPSR in debug state31511.8.5 Privilege31511.8.6 Accessing registers and memory31511.8.7 Coprocessor instructions31611.8.8 Effect of debug state on non-invasive debug31611.8.9 Effects of debug events on processor registers31611.8.10 Exceptions in debug state31611.8.11 Leaving debug state31711.9 Cache debug31911.9.1 Cache pollution in debug state31911.9.2 Cache coherency in debug state31911.9.3 Cache usage profiling31911.10 External debug interface32011.10.1 APB signals32011.10.2 Miscellaneous debug signals32011.10.3 Authentication signals32111.11 Using the debug functionality32311.11.1 Debug communications channel32411.11.2 Programming breakpoints and watchpoints32611.11.3 Single-stepping32911.11.4 Debug state entry33011.11.5 Debug state exit33111.11.6 Accessing registers and memory in debug state33211.12 Debugging systems with energy management capabilities34011.12.1 Emulating power down340FPU Programmer’s Model34212.1 About the FPU programmer’s model34312.1.1 FPU functionality34312.1.2 About the VFPv3-D16 architecture34312.2 General-purpose registers34412.2.1 FPU views of the register bank34412.3 System registers34512.3.1 Floating-Point System ID Register, FPSID34612.3.2 Floating-Point Status and Control Register, FPSCR34712.3.3 Floating-Point Exception Register, FPEXC34812.3.4 Media and VFP Feature Registers, MVFR0 and MVFR134912.4 Modes of operation35112.4.1 Full-compliance mode35112.4.2 Flush-to-zero mode35112.4.3 Default NaN mode35112.5 Compliance with the IEEE 754 standard35212.5.1 Complete implementation of the IEEE 754 standard35212.5.2 IEEE 754 standard implementation choices35212.5.3 Exceptions354Integration Test Registers35513.1 About Integration Test Registers35613.2 Programming and reading Integration Test Registers35713.2.1 Software access using APB35713.3 Summary of the processor registers used for integration testing35813.4 Processor integration testing35913.4.1 Using the Integration Test Registers36013.4.2 Performing integration testing36013.4.3 ITETMIF Register (ETM interface)36113.4.4 ITMISCOUT Register (Miscellaneous Outputs)36213.4.5 ITMISCIN Register (Miscellaneous Inputs)36213.4.6 Integration Mode Control Register (ITCTRL)363Cycle Timings and Interlock Behavior36514.1 About cycle timings and interlock behavior36714.1.1 Instruction execution overview36714.1.2 Conditional instructions36814.1.3 Flag-setting instructions36814.1.4 Definition of terms36814.1.5 Assembler language syntax36914.2 Register interlock examples37014.3 Data processing instructions37114.3.1 Cycle counts if destination is not PC37114.3.2 Cycle counts if destination is the PC37114.3.3 Example interlocks37214.4 QADD, QDADD, QSUB, and QDSUB instructions37314.5 Media data-processing37414.6 Sum of Absolute Differences (SAD)37514.6.1 Example interlocks37514.7 Multiplies37614.8 Divide37814.9 Branches37914.10 Processor state updating instructions38014.11 Single load and store instructions38114.11.1 Base register update38214.12 Load and Store Double instructions38414.13 Load and Store Multiple instructions38514.13.1 Load and Store Multiples, other than load multiples including the PC38514.13.2 Load Multiples, where the PC is in the register list38614.13.3 Example Interlocks38614.14 RFE and SRS instructions38814.15 Synchronization instructions38914.16 Coprocessor instructions39014.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions39114.18 Miscellaneous instructions39214.19 Floating-point register transfer instructions39314.20 Floating-point load/store instructions39414.21 Floating-point single-precision data processing instructions39614.22 Floating-point double-precision data processing instructions39714.23 Dual issue39814.23.1 Dual issue rules39814.23.2 Permitted combinations399AC Characteristics40115.1 Processor timing40215.2 Processor timing parameters40315.2.1 Input port timing parameters40315.2.2 Output ports timing parameters408Processor Signal Descriptions414A.1 About the processor signal descriptions415A.2 Global signals416A.3 Configuration signals417A.4 Interrupt signals, including VIC interface signals420A.5 L2 interface signals421A.5.1 AXI master port421A.5.2 AXI master port error detection signals423A.5.3 AXI slave port423A.5.4 AXI slave port error detection signals425A.6 TCM interface signals426A.7 Dual core interface signals429A.8 Debug interface signals430A.9 ETM interface signals432A.10 Test signals433A.11 MBIST signals434A.12 Validation signals435A.13 FPU signals436ECC Schemes437B.1 ECC scheme selection guidelines438Revisions439Glossary442Tamaño: 3 MBPáginas: 456Language: EnglishManuales abiertas