Hoja De Datos (ATSAM4S-XSTK)Tabla de contenidosPreface1Table of Contents21. Introduction31.1. Features31.2. Kit overview32. Getting started52.1. Quick-start52.2. Connecting the kit52.3. Design documentation and related links53. Xplained Pro63.1. Embedded Debugger63.2. Hardware identification system63.3. Power supply73.3.1. Measuring SAM4S power consumption73.4. Standard headers and connectors73.4.1. Xplained Pro extension header73.4.2. Xplained Pro LCD connector83.4.3. Power header104. Hardware user guide114.1. Connectors114.1.1. I/O extension headers114.1.2. LCD extension connector124.1.3. Other headers144.2. Peripherals144.2.1. NAND Flash144.2.2. SD Card connector154.2.3. Crystals154.2.4. Mechanical buttons164.2.5. LED164.2.6. Analog reference164.3. Embedded Debugger implementation164.3.1. Serial Wire Debug164.3.2. Virtual COM port164.3.3. Atmel Data Gateway Interface175. Hardware revision history and known issues185.1. Identifying product ID and revision185.2. Revision 5185.3. Revision 4186. Document revision history197. Evaluation board/kit important notice20Tamaño: 800 KBPáginas: 21Language: EnglishManuales abiertas
Hoja De Datos (ATSAM4S-XSTK)Tabla de contenidosDescription11. Features11.1 Configuration Summary32. Block Diagram43. Signal Description84. Package and Pinout124.1 SAM4SD32/SD16/SA16/S16/S8C Package and Pinout124.1.1 100-lead LQFP Package Outline124.1.2 100-ball TFBGA Package Outline124.1.3 100-ball VFBGA Package Outline134.1.4 100-lead LQFP Pinout144.1.5 100-ball TFBGA Pinout154.1.6 100-ball VFBGA Pinout164.2 SAM4SD32/SD16/SA16/S16/S8 Package and Pinout174.2.1 64-lead LQFP Package Outline174.2.2 64-lead QFN Package Outline174.2.3 64-ball WLCSP Package Outline174.2.4 64-lead LQFP and QFN Pinout184.2.5 64-ball WLCSP Pinout195. Power Considerations205.1 Power Supplies205.2 Voltage Regulator205.3 Typical Powering Schematics205.4 Active Mode225.5 Low-power Modes225.5.1 Backup Mode225.5.2 Wait Mode225.5.3 Sleep Mode235.5.4 Low-power Mode Summary Table245.6 Wake-up Sources255.7 Fast Start-up266. Input/Output Lines276.1 General Purpose I/O Lines276.2 System I/O Lines276.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins286.3 Test Pin286.4 NRST Pin296.5 ERASE Pin297. Product Mapping308. Memories318.1 Embedded Memories318.1.1 Internal SRAM318.1.2 Internal ROM318.1.3 Embedded Flash318.1.3.1 Flash Overview318.1.3.2 Enhanced Embedded Flash Controller338.1.3.3 Flash Speed338.1.3.4 Lock Regions338.1.3.5 Security Bit Feature348.1.3.6 Calibration Bits348.1.3.7 Unique Identifier348.1.3.8 User Signature348.1.3.9 Fast Flash Programming Interface348.1.3.10 SAM-BA Boot348.1.3.11 GPNVM Bits348.1.4 Boot Strategies358.2 External Memories358.2.1 Static Memory Controller359. Real Time Event Management369.1 Embedded Characteristics369.2 Real Time Event Mapping List3710. System Controller3810.1 System Controller and Peripheral Mapping4010.2 Power-on-Reset, Brownout and Supply Monitor4010.2.1 Power-on-Reset4010.2.2 Brownout Detector on VDDCORE4010.2.3 Supply Monitor on VDDIO4011. Peripherals4111.1 Peripheral Identifiers4111.2 Peripheral Signal Multiplexing on I/O Lines4211.2.1 PIO Controller A Multiplexing4311.2.2 PIO Controller B Multiplexing4411.2.3 PIO Controller C Multiplexing4512. ARM Cortex-M44712.1 Description4712.1.1 System Level Interface4712.1.2 Integrated Configurable Debug4712.2 Embedded Characteristics4812.3 Block Diagram4812.4 Cortex-M4 Models4912.4.1 Programmers Model4912.4.1.1 Processor Modes and Privilege Levels for Software Execution4912.4.1.2 Stacks4912.4.1.3 Core Registers5012.4.1.4 General-purpose Registers5112.4.1.5 Stack Pointer5112.4.1.6 Link Register5112.4.1.7 Program Counter5112.4.1.8 Program Status Register5212.4.1.9 Application Program Status Register5312.4.1.10 Interrupt Program Status Register5412.4.1.11 Execution Program Status Register5512.4.1.12 Exception Mask Registers5612.4.1.13 Priority Mask Register5612.4.1.14 Fault Mask Register5712.4.1.15 Base Priority Mask Register5812.4.1.16 CONTROL Register5912.4.1.17 Exceptions and Interrupts6012.4.1.18 Data Types6012.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)6012.4.2 Memory Model6112.4.2.1 Memory Regions, Types and Attributes6112.4.2.2 Memory System Ordering of Memory Accesses6212.4.2.3 Behavior of Memory Accesses6312.4.2.4 Software Ordering of Memory Accesses6412.4.2.5 Bit-banding6412.4.2.6 Memory Endianness6612.4.2.7 Synchronization Primitives6712.4.2.8 Programming Hints for the Synchronization Primitives6812.4.3 Exception Model6912.4.3.1 Exception States6912.4.3.2 Exception Types6912.4.3.3 Exception Handlers7112.4.3.4 Vector Table7112.4.3.5 Exception Priorities7212.4.3.6 Interrupt Priority Grouping7212.4.3.7 Exception Entry and Return7212.4.3.8 Fault Handling7512.5 Power Management7812.5.1 Entering Sleep Mode7812.5.1.1 Wait for Interrupt7812.5.1.2 Sleep-on-exit7812.5.2 Wakeup from Sleep Mode7812.5.2.1 Wakeup from WFI or Sleep-on-exit7812.5.3 Power Management Programming Hints7812.6 Cortex-M4 Instruction Set7912.6.1 Instruction Set Summary7912.6.2 CMSIS Functions8512.6.3 Instruction Descriptions8612.6.3.1 Operands8612.6.3.2 Restrictions when Using PC or SP8612.6.3.3 Flexible Second Operand8612.6.3.4 Shift Operations8712.6.3.5 Address Alignment8912.6.3.6 PC-relative Expressions8912.6.3.7 Conditional Execution8912.6.3.8 Instruction Width Selection9112.6.4 Memory Access Instructions9212.6.4.1 ADR9312.6.4.2 LDR and STR, Immediate Offset9412.6.4.3 LDR and STR, Register Offset9512.6.4.4 LDR and STR, Unprivileged9712.6.4.5 LDR, PC-relative9812.6.4.6 LDM and STM9912.6.4.7 PUSH and POP10112.6.4.8 LDREX and STREX10212.6.4.9 CLREX10312.6.5 General Data Processing Instructions10412.6.5.1 ADD, ADC, SUB, SBC, and RSB10612.6.5.2 AND, ORR, EOR, BIC, and ORN10812.6.5.3 ASR, LSL, LSR, ROR, and RRX10912.6.5.4 CLZ11012.6.5.5 CMP and CMN11012.6.5.6 MOV and MVN11112.6.5.7 MOVT11212.6.5.8 REV, REV16, REVSH, and RBIT11312.6.5.9 SADD16 and SADD811412.6.5.10 SHADD16 and SHADD811512.6.5.11 SHASX and SHSAX11612.6.5.12 SHSUB16 and SHSUB811712.6.5.13 SSUB16 and SSUB811812.6.5.14 SASX and SSAX11912.6.5.15 TST and TEQ12012.6.5.16 UADD16 and UADD812112.6.5.17 UASX and USAX12212.6.5.18 UHADD16 and UHADD812312.6.5.19 UHASX and UHSAX12412.6.5.20 UHSUB16 and UHSUB812512.6.5.21 SEL12612.6.5.22 USAD812712.6.5.23 USADA812812.6.5.24 USUB16 and USUB812912.6.6 Multiply and Divide Instructions13012.6.6.1 MUL, MLA, and MLS13112.6.6.2 UMULL, UMAAL, UMLAL13212.6.6.3 SMLA and SMLAW13312.6.6.4 SMLAD13512.6.6.5 SMLAL and SMLALD13612.6.6.6 SMLSD and SMLSLD13712.6.6.7 SMMLA and SMMLS13912.6.6.8 SMMUL14012.6.6.9 SMUAD and SMUSD14012.6.6.10 SMUL and SMULW14112.6.6.11 UMULL, UMLAL, SMULL, and SMLAL14312.6.6.12 SDIV and UDIV14412.6.7 Saturating Instructions14512.6.7.1 SSAT and USAT14612.6.7.2 SSAT16 and USAT1614712.6.7.3 QADD and QSUB14812.6.7.4 QASX and QSAX14912.6.7.5 QDADD and QDSUB15012.6.7.6 UQASX and UQSAX15112.6.7.7 UQADD and UQSUB15212.6.8 Packing and Unpacking Instructions15312.6.8.1 PKHBT and PKHTB15412.6.8.2 SXT and UXT15512.6.8.3 SXTA and UXTA15512.6.9 Bitfield Instructions15712.6.9.1 BFC and BFI15812.6.9.2 SBFX and UBFX15912.6.9.3 SXT and UXT16012.6.10 Branch and Control Instructions16112.6.10.1 B, BL, BX, and BLX16212.6.10.2 CBZ and CBNZ16412.6.10.3 IT16512.6.10.4 TBB and TBH16612.6.11 Miscellaneous Instructions16812.6.11.1 BKPT16912.6.11.2 CPS16912.6.11.3 DMB17012.6.11.4 DSB17012.6.11.5 ISB17012.6.11.6 MRS17112.6.11.7 MSR17112.6.11.8 NOP17212.6.11.9 SEV17212.6.11.10 SVC17312.6.11.11 WFI17312.7 Cortex-M4 Core Peripherals17412.7.1 Peripherals17412.7.2 Address Map17412.8 Nested Vectored Interrupt Controller (NVIC)17512.8.1 Level-sensitive Interrupts17512.8.1.1 Hardware and Software Control of Interrupts17512.8.2 NVIC Design Hints and Tips17512.8.2.1 NVIC Programming Hints17612.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface17712.8.3.1 Interrupt Set-enable Registers17812.8.3.2 Interrupt Clear-enable Registers17912.8.3.3 Interrupt Set-pending Registers18012.8.3.4 Interrupt Clear-pending Registers18112.8.3.5 Interrupt Active Bit Registers18212.8.3.6 Interrupt Priority Registers18312.8.3.7 Software Trigger Interrupt Register18412.9 System Control Block (SCB)18512.9.1 System Control Block (SCB) User Interface18612.9.1.1 Auxiliary Control Register18712.9.1.2 CPUID Base Register18812.9.1.3 Interrupt Control and State Register18912.9.1.4 Vector Table Offset Register19112.9.1.5 Application Interrupt and Reset Control Register19212.9.1.6 System Control Register19412.9.1.7 Configuration and Control Register19512.9.1.8 System Handler Priority Registers19712.9.1.9 System Handler Priority Register 119712.9.1.10 System Handler Priority Register 219812.9.1.11 System Handler Priority Register 319812.9.1.12 System Handler Control and State Register19912.9.1.13 Configurable Fault Status Register20112.9.1.14 Configurable Fault Status Register (Byte Access)20512.9.1.15 Hard Fault Status Register20612.9.1.16 MemManage Fault Address Register20712.9.1.17 Bus Fault Address Register20812.10 System Timer (SysTick)20912.10.1 System Timer (SysTick) User Interface20912.10.1.1 SysTick Control and Status21012.10.1.2 SysTick Reload Value Registers21112.10.1.3 SysTick Current Value Register21212.10.1.4 SysTick Calibration Value Register21312.11 Memory Protection Unit (MPU)21412.11.1 MPU Access Permission Attributes21412.11.1.1 MPU Mismatch21612.11.1.2 Updating an MPU Region21612.11.1.3 Updating an MPU Region Using Separate Words21612.11.1.4 Updating an MPU Region Using Multi-word Writes21712.11.1.5 Subregions21812.11.1.6 Example of SRD Use21812.11.1.7 MPU Design Hints And Tips21812.11.2 Memory Protection Unit (MPU) User Interface22012.11.2.1 MPU Type Register22112.11.2.2 MPU Control Register22212.11.2.3 MPU Region Number Register22412.11.2.4 MPU Region Base Address Register22512.11.2.5 MPU Region Attribute and Size Register22612.12 Glossary22813. Debug and Test Features23313.1 Description23313.2 Embedded Characteristics23313.3 Application Examples23413.3.1 Debug Environment23413.3.2 Test Environment23413.4 Debug and Test Pin Description23513.5 Functional Description23613.5.1 Test Pin23613.5.2 Debug Architecture23613.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)23613.5.3.1 SW-DP and JTAG-DP Selection Mechanism23713.5.4 FPB (Flash Patch Breakpoint)23713.5.5 DWT (Data Watchpoint and Trace)23713.5.6 ITM (Instrumentation Trace Macrocell)23813.5.6.1 How to Configure the ITM23813.5.6.2 Asynchronous Mode23813.5.6.3 5.4.3. How to Configure the TPIU23813.5.7 IEEE® 1149.1 JTAG Boundary Scan23913.5.7.1 JTAG Boundary-scan Register23913.5.8 ID Code Register24014. Reset Controller (RSTC)24114.1 Description24114.2 Embedded Characteristics24114.3 Block Diagram24114.4 Functional Description24214.4.1 Reset Controller Overview24214.4.2 NRST Manager24214.4.2.1 NRST Signal or Interrupt24214.4.2.2 NRST External Reset Control24314.4.3 Brownout Manager24314.4.4 Reset States24314.4.4.1 General Reset24314.4.4.2 Backup Reset24414.4.4.3 User Reset24414.4.4.4 Software Reset24514.4.4.5 Watchdog Reset24614.4.5 Reset State Priorities24714.4.6 Reset Controller Status Register24814.5 Reset Controller (RSTC) User Interface24914.5.1 Reset Controller Control Register25014.5.2 Reset Controller Status Register25114.5.3 Reset Controller Mode Register25215. Real-time Timer (RTT)25315.1 Description25315.2 Embedded Characteristics25315.3 Block Diagram25315.4 Functional Description25315.5 Real-time Timer (RTT) User Interface25515.5.1 Real-time Timer Mode Register25615.5.2 Real-time Timer Alarm Register25715.5.3 Real-time Timer Value Register25715.5.4 Real-time Timer Status Register25816. Real-time Clock (RTC)25916.1 Description25916.2 Embedded Characteristics25916.3 Block Diagram26016.4 Product Dependencies26016.4.1 Power Management26016.4.2 Interrupt26016.5 Functional Description26116.5.1 Reference Clock26116.5.2 Timing26116.5.3 Alarm26116.5.4 Error Checking when Programming26116.5.5 RTC Internal Free Running Counter Error Checking26216.5.6 Updating Time/Calendar26216.5.7 RTC Accurate Clock Calibration26416.5.8 Waveform Generation26416.6 Real-time Clock (RTC) User Interface26616.6.1 RTC Control Register26716.6.2 RTC Mode Register26816.6.3 RTC Time Register27116.6.4 RTC Calendar Register27216.6.5 RTC Time Alarm Register27316.6.6 RTC Calendar Alarm Register27416.6.7 RTC Status Register27516.6.8 RTC Status Clear Command Register27616.6.9 RTC Interrupt Enable Register27716.6.10 RTC Interrupt Disable Register27816.6.11 RTC Interrupt Mask Register27916.6.12 RTC Valid Entry Register28017. Watchdog Timer (WDT)28117.1 Description28117.2 Embedded Characteristics28117.3 Block Diagram28117.4 Functional Description28117.5 Watchdog Timer (WDT) User Interface28317.5.1 Watchdog Timer Control Register28417.5.2 Watchdog Timer Mode Register28517.5.3 Watchdog Timer Status Register28618. Supply Controller (SUPC)28718.1 Description28718.2 Embedded Characteristics28718.3 Block Diagram28818.4 Supply Controller Functional Description28918.4.1 Supply Controller Overview28918.4.2 Slow Clock Generator29018.4.3 Voltage Regulator Control/Backup Low Power Mode29018.4.4 Supply Monitor29118.4.5 Backup Power Supply Reset29218.4.5.1 Raising the Backup Power Supply29218.4.6 Core Reset29318.4.6.1 Supply Monitor Reset29318.4.6.2 Brownout Detector Reset29318.4.7 Wake Up Sources29318.4.7.1 Wake Up Inputs29418.4.7.2 Low Power Debouncer Inputs29518.4.7.3 Clock Alarms29618.4.7.4 Supply Monitor Detection29618.4.8 Low Power Tamper Detection Inputs29618.5 Supply Controller (SUPC) User Interface29718.5.1 System Controller (SYSC) User Interface29718.5.2 Supply Controller (SUPC) User Interface29718.5.3 Supply Controller Control Register29818.5.4 Supply Controller Supply Monitor Mode Register29918.5.5 Supply Controller Mode Register30018.5.6 Supply Controller Wake Up Mode Register30118.5.7 System Controller Wake Up Inputs Register30318.5.8 Supply Controller Status Register30418.5.9 System Controller Write Protect Mode Register30619. General Purpose Backup Registers (GPBR)30719.1 Description30719.2 Embedded Characteristics30719.3 General Purpose Backup Registers (GPBR) User Interface30719.3.1 General Purpose Backup Register x30820. Enhanced Embedded Flash Controller (EEFC)30920.1 Description30920.2 Embedded Characteristics30920.3 Product Dependencies30920.3.1 Power Management30920.3.2 Interrupt Sources30920.4 Functional Description30920.4.1 Embedded Flash Organization30920.4.2 Read Operations31020.4.2.1 128-bit or 64-bit Access Mode31020.4.2.2 Code Read Optimization31120.4.2.3 Code Loops Optimization31120.4.2.4 Data Read Optimization31220.4.3 Flash Commands31320.4.3.1 Getting Embedded Flash Descriptor31420.4.3.2 Write Commands31520.4.3.3 Erase Commands31620.4.3.4 Lock Bit Protection31720.4.3.5 GPNVM Bit31820.4.3.6 Calibration Bit31920.4.3.7 Security Bit Protection31920.4.3.8 Unique Identifier31920.4.3.9 User Signature32020.5 Enhanced Embedded Flash Controller (EEFC) User Interface32120.5.1 EEFC Flash Mode Register32220.5.2 EEFC Flash Command Register32320.5.3 EEFC Flash Status Register32520.5.4 EEFC Flash Result Register32621. Fast Flash Programming Interface (FFPI)32721.1 Description32721.2 Parallel Fast Flash Programming32721.2.1 Device Configuration32721.2.2 Signal Names32821.2.3 Entering Programming Mode32921.2.4 Programmer Handshaking32921.2.4.1 Write Handshaking32921.2.4.2 Read Handshaking33021.2.5 Device Operations33121.2.5.1 Flash Read Command33121.2.5.2 Flash Write Command33121.2.5.3 Flash Full Erase Command33221.2.5.4 Flash Lock Commands33221.2.5.5 Flash General-purpose NVM Commands33321.2.5.6 Flash Security Bit Command33321.2.5.7 Memory Write Command33421.2.5.8 Get Version Command33422. Cortex M Cache Controller (CMCC) (ONLY FOR SAM4SD32/SD16/SA16)33522.1 Description33522.2 Embedded Characteristics33522.3 Block Diagram33522.4 Functional Description33622.4.1 Cache Operation33622.4.2 Cache Maintenance33622.4.2.1 Cache Invalidate by Line Operation33622.4.2.2 Cache Invalidate All Operation33622.4.3 Cache Performance Monitoring33622.5 Cortex M Cache Controller (CMCC) User Interface33722.5.1 Cache Controller Type Register33822.5.2 Cache Controller Configuration Register34022.5.3 Cache Controller Control Register34122.5.4 Cache Controller Status Register34222.5.5 Cache Controller Maintenance Register 034322.5.6 Cache Controller Maintenance Register 134422.5.7 Cache Controller Monitor Configuration Register34522.5.8 Cache Controller Monitor Enable Register34622.5.9 Cache Controller Monitor Control Register34722.5.10 Cache Controller Monitor Status Register34823. Cyclic Redundancy Check Calculation Unit (CRCCU)34923.1 Description34923.2 Embedded Characteristics34923.3 CRCCU Block Diagram34923.4 Product Dependencies35023.4.1 Power Management35023.4.2 Interrupt Source35023.5 CRCCU Functional Description35023.5.1 CRC Calculation Unit description35023.5.2 CRC Calculation Unit Operation35023.6 Transfer Control Registers Memory Mapping35123.6.1 Transfer Address Register35223.6.2 Transfer Control Register35323.6.3 Transfer Reference Register35423.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface35523.7.1 CRCCU Descriptor Base Address Register35623.7.2 CRCCU DMA Enable Register35723.7.3 CRCCU DMA Disable Register35823.7.4 CRCCU DMA Status Register35923.7.5 CRCCU DMA Interrupt Enable Register36023.7.6 CRCCU DMA Interrupt Disable Register36123.7.7 CRCCU DMA Interrupt Mask Register36223.7.8 CRCCU DMA Interrupt Status Register36323.7.9 CRCCU Control Register36423.7.10 CRCCU Mode Register36523.7.11 CRCCU Status Register36623.7.12 CRCCU Interrupt Enable Register36723.7.13 CRCCU Interrupt Disable Register36823.7.14 CRCCU Interrupt Mask Register36923.7.15 CRCCU Interrupt Status Register37024. SAM4S Boot Program37124.1 Description37124.2 Hardware and Software Constraints37124.3 Flow Diagram37124.4 Device Initialization37224.5 SAM-BA Monitor37324.5.1 UART0 Serial Port37424.5.2 Xmodem Protocol37424.5.3 USB Device Port37424.5.3.1 Enumeration Process37524.5.3.2 Communication Endpoints37524.5.4 In Application Programming (IAP) Feature37625. Bus Matrix (MATRIX)37725.1 Description37725.2 Embedded Characteristics37725.2.1 Matrix Masters37725.2.2 Matrix Slaves37725.2.3 Master to Slave Access37825.3 Memory Mapping37825.4 Special Bus Granting Techniques37825.4.1 No Default Master37825.4.2 Last Access Master37825.4.3 Fixed Default Master37825.5 Arbitration37925.5.1 Arbitration Rules37925.5.1.1 Undefined Length Burst Arbitration37925.5.1.2 Slot Cycle Limit Arbitration37925.5.2 Round-Robin Arbitration37925.5.2.1 Round-Robin arbitration without default master38025.5.2.2 Round-Robin arbitration with last access master38025.5.2.3 Round-Robin arbitration with fixed default master38025.5.3 Fixed Priority Arbitration38025.6 System I/O Configuration38025.7 Write Protect Registers38025.8 Bus Matrix (MATRIX) User Interface38125.8.1 Bus Matrix Master Configuration Registers38225.8.2 Bus Matrix Slave Configuration Registers38325.8.3 Bus Matrix Priority Registers For Slaves38425.8.4 System I/O Configuration Register38525.8.5 SMC NAND Flash Chip select Configuration Register38625.8.6 Write Protect Mode Register38725.8.7 Write Protect Status Register38826. Static Memory Controller (SMC)38926.1 Description38926.2 Embedded Characteristics38926.3 I/O Lines Description39026.4 Product Dependencies39026.4.1 I/O Lines39026.4.2 Power Management39026.5 External Memory Mapping39026.6 Connection to External Devices39126.6.1 Data Bus Width39126.6.1.1 NAND Flash Support39126.7 Application Example39326.7.1 Implementation Examples39326.7.1.1 8-bit NAND Flash39426.7.1.2 NOR Flash39526.8 Standard Read and Write Protocols39526.8.1 Read Waveforms39526.8.1.1 NRD Waveform39626.8.1.2 NCS Waveform39626.8.1.3 Read Cycle39626.8.1.4 Null Delay Setup and Hold39726.8.1.5 Null Pulse39726.8.2 Read Mode39726.8.2.1 Read is Controlled by NRD (READ_MODE = 1):39726.8.2.2 Read is Controlled by NCS (READ_MODE = 0)39826.8.3 Write Waveforms39926.8.3.1 NWE Waveforms39926.8.3.2 NCS Waveforms39926.8.3.3 Write Cycle39926.8.3.4 Null Delay Setup and Hold40026.8.3.5 Null Pulse40026.8.4 Write Mode40026.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):40026.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)40126.8.5 Write Protected Registers40126.8.6 Coding Timing Parameters40226.8.7 Reset Values of Timing Parameters40226.8.8 Usage Restriction40226.9 Scrambling/Unscrambling Function40326.10 Automatic Wait States40326.10.1 Chip Select Wait States40326.10.2 Early Read Wait State40426.10.3 Reload User Configuration Wait State40626.10.3.1 User Procedure40626.10.3.2 Slow Clock Mode Transition40726.10.4 Read to Write Wait State40726.11 Data Float Wait States40826.11.1 READ_MODE40826.11.2 TDF Optimization Enabled (TDF_MODE = 1)40926.11.3 TDF Optimization Disabled (TDF_MODE = 0)41026.12 External Wait41226.12.1 Restriction41226.12.2 Frozen Mode41326.12.3 Ready Mode41526.12.4 NWAIT Latency and Read/Write Timings41726.13 Slow Clock Mode41826.13.1 Slow Clock Mode Waveforms41826.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode41826.14 Asynchronous Page Mode41926.14.1 Protocol and Timings in Page Mode42026.14.2 Page Mode Restriction42126.14.3 Sequential and Non-sequential Accesses42126.15 Static Memory Controller (SMC) User Interface42226.15.1 SMC Setup Register42326.15.2 SMC Pulse Register42426.15.3 SMC Cycle Register42526.15.4 SMC MODE Register42626.15.5 SMC OCMS Mode Register42826.15.6 SMC OCMS Key1 Register42926.15.7 SMC OCMS Key2 Register43026.15.8 SMC Write Protect Mode Register43126.15.9 SMC Write Protect Status Register43227. Peripheral DMA Controller (PDC)43327.1 Description43327.2 Embedded Characteristics43327.3 Block Diagram43427.4 Functional Description43527.4.1 Configuration43527.4.2 Memory Pointers43527.4.3 Transfer Counters43627.4.4 Data Transfers43627.4.5 PDC Flags and Peripheral Status Register43727.4.5.1 Receive Transfer End43727.4.5.2 Transmit Transfer End43727.4.5.3 Receive Buffer Full43727.4.5.4 Transmit Buffer Empty43727.5 Peripheral DMA Controller (PDC) User Interface43827.5.1 Receive Pointer Register43927.5.2 Receive Counter Register44027.5.3 Transmit Pointer Register44127.5.4 Transmit Counter Register44227.5.5 Receive Next Pointer Register44327.5.6 Receive Next Counter Register44427.5.7 Transmit Next Pointer Register44527.5.8 Transmit Next Counter Register44627.5.9 Transfer Control Register44727.5.10 Transfer Status Register44828. Power Management Controller (PMC)44928.1 Clock Generator44928.1.1 Description44928.1.2 Embedded Characteristics44928.1.3 Block Diagram45028.1.4 Slow Clock45028.1.4.1 Slow Clock RC Oscillator45128.1.4.2 Slow Clock Crystal Oscillator45128.1.5 Main Clock45228.1.5.1 Fast RC Oscillator45228.1.5.2 Fast RC Oscillator Clock Frequency Adjustment45328.1.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator45328.1.5.4 Main Clock Oscillator Selection45428.1.5.5 Software Sequence to Detect the Presence of Fast Crystal45428.1.5.6 Main Clock Frequency Counter45528.1.6 Divider and PLL Block45528.1.6.1 Divider and Phase Lock Loop Programming45628.2 Power Management Controller (PMC)45828.2.1 Description45828.2.2 Embedded Characteristics45828.2.3 Block Diagram45928.2.4 Master Clock Controller45928.2.5 Processor Clock Controller46028.2.6 SysTick Clock46028.2.7 USB Clock Controller46028.2.8 Peripheral Clock Controller46128.2.9 Free Running Processor Clock46128.2.10 Programmable Clock Output Controller46128.2.11 Fast Start-up46128.2.12 Main Crystal Clock Failure Detector46328.2.13 Programming Sequence46428.2.14 Clock Switching Details46628.2.14.1 Master Clock Switching Timings46628.2.14.2 Clock Switching Waveforms46728.2.15 Write Protection Registers46928.2.16 Power Management Controller (PMC) User Interface47028.2.16.1 PMC System Clock Enable Register47228.2.16.2 PMC System Clock Disable Register47328.2.16.3 PMC System Clock Status Register47428.2.16.4 PMC Peripheral Clock Enable Register 047528.2.16.5 PMC Peripheral Clock Disable Register 047628.2.16.6 PMC Peripheral Clock Status Register 047728.2.16.7 PMC Clock Generator Main Oscillator Register47828.2.16.8 PMC Clock Generator Main Clock Frequency Register48028.2.16.9 PMC Clock Generator PLLA Register48128.2.16.10 PMC Clock Generator PLLB Register48228.2.16.11 PMC Master Clock Register48328.2.16.12 PMC USB Clock Register48528.2.16.13 PMC Programmable Clock Register48628.2.16.14 PMC Interrupt Enable Register48728.2.16.15 PMC Interrupt Disable Register48828.2.16.16 PMC Status Register48928.2.16.17 PMC Interrupt Mask Register49128.2.16.18 PMC Fast Start-up Mode Register49228.2.16.19 PMC Fast Start-up Polarity Register49328.2.16.20 PMC Fault Output Clear Register49428.2.16.21 PMC Write Protect Mode Register49528.2.16.22 PMC Write Protect Status Register49628.2.16.23 PMC Peripheral Clock Enable Register 149728.2.16.24 PMC Peripheral Clock Disable Register 149728.2.16.25 PMC Peripheral Clock Status Register 149828.2.16.26 PMC Oscillator Calibration Register49929. Chip Identifier (CHIPID)50129.1 Description50129.2 Embedded Characteristics50129.3 Chip Identifier (CHIPID) User Interface50129.3.1 Chip ID Register50229.3.2 Chip ID Extension Register50630. Parallel Input/Output (PIO) Controller50730.1 Description50730.2 Embedded Characteristics50730.3 Block Diagram50830.4 Product Dependencies50930.4.1 Pin Multiplexing50930.4.2 External Interrupt Lines50930.4.3 Power Management50930.4.4 Interrupt Generation50930.5 Functional Description51030.5.1 Pull-up and Pull-down Resistor Control51130.5.2 I/O Line or Peripheral Function Selection51130.5.3 Peripheral A or B or C or D Selection51130.5.4 Output Control51230.5.5 Synchronous Data Output51230.5.6 Multi Drive Control (Open Drain)51230.5.7 Output Line Timings51230.5.8 Inputs51330.5.9 Input Glitch and Debouncing Filters51330.5.10 Input Edge/Level Interrupt51430.5.10.1 Example51530.5.10.2 Interrupt Mode Configuration51630.5.10.3 Edge or Level Detection Configuration51630.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration.51630.5.11 I/O Lines Lock51630.5.12 Programmable Schmitt Trigger51630.5.13 Parallel Capture Mode51730.5.13.1 Overview51730.5.13.2 Functional Description51730.5.13.3 Restrictions51930.5.13.4 Programming Sequence51930.5.14 Write Protection Registers52030.6 I/O Lines Programming Example52130.7 Parallel Input/Output Controller (PIO) User Interface52230.7.1 PIO Enable Register52530.7.2 PIO Disable Register52530.7.3 PIO Status Register52630.7.4 PIO Output Enable Register52630.7.5 PIO Output Disable Register52730.7.6 PIO Output Status Register52730.7.7 PIO Input Filter Enable Register52830.7.8 PIO Input Filter Disable Register52830.7.9 PIO Input Filter Status Register52930.7.10 PIO Set Output Data Register52930.7.11 PIO Clear Output Data Register53030.7.12 PIO Output Data Status Register53030.7.13 PIO Pin Data Status Register53130.7.14 PIO Interrupt Enable Register53130.7.15 PIO Interrupt Disable Register53230.7.16 PIO Interrupt Mask Register53230.7.17 PIO Interrupt Status Register53330.7.18 PIO Multi-driver Enable Register53330.7.19 PIO Multi-driver Disable Register53430.7.20 PIO Multi-driver Status Register53430.7.21 PIO Pull Up Disable Register53530.7.22 PIO Pull Up Enable Register53530.7.23 PIO Pull Up Status Register53630.7.24 PIO Peripheral ABCD Select Register 153730.7.25 PIO Peripheral ABCD Select Register 253830.7.26 PIO Input Filter Slow Clock Disable Register53930.7.27 PIO Input Filter Slow Clock Enable Register53930.7.28 PIO Input Filter Slow Clock Status Register54030.7.29 PIO Slow Clock Divider Debouncing Register54030.7.30 PIO Pad Pull Down Disable Register54130.7.31 PIO Pad Pull Down Enable Register54130.7.32 PIO Pad Pull Down Status Register54230.7.33 PIO Output Write Enable Register54330.7.34 PIO Output Write Disable Register54330.7.35 PIO Output Write Status Register54430.7.36 PIO Additional Interrupt Modes Enable Register54430.7.37 PIO Additional Interrupt Modes Disable Register54530.7.38 PIO Additional Interrupt Modes Mask Register54530.7.39 PIO Edge Select Register54630.7.40 PIO Level Select Register54630.7.41 PIO Edge/Level Status Register54730.7.42 PIO Falling Edge/Low Level Select Register54730.7.43 PIO Rising Edge/High Level Select Register54830.7.44 PIO Fall/Rise - Low/High Status Register54830.7.45 PIO Lock Status Register54930.7.46 PIO Write Protect Mode Register55030.7.47 PIO Write Protect Status Register55130.7.48 PIO Schmitt Trigger Register55230.7.49 PIO Parallel Capture Mode Register55330.7.50 PIO Parallel Capture Interrupt Enable Register55430.7.51 PIO Parallel Capture Interrupt Disable Register55530.7.52 PIO Parallel Capture Interrupt Mask Register55630.7.53 PIO Parallel Capture Interrupt Status Register55730.7.54 PIO Parallel Capture Reception Holding Register55831. Synchronous Serial Controller (SSC)55931.1 Description55931.2 Embedded Characteristics55931.3 Block Diagram56031.4 Application Block Diagram56031.5 Pin Name List56131.6 Product Dependencies56131.6.1 I/O Lines56131.6.2 Power Management56131.6.3 Interrupt56131.7 Functional Description56231.7.1 Clock Management56231.7.1.1 Clock Divider56331.7.1.2 Transmitter Clock Management56331.7.1.3 Receiver Clock Management56431.7.1.4 Serial Clock Ratio Considerations56431.7.2 Transmitter Operations56531.7.3 Receiver Operations56531.7.4 Start56631.7.5 Frame Sync56731.7.5.1 Frame Sync Data56831.7.5.2 Frame Sync Edge Detection56831.7.6 Receive Compare Modes56831.7.6.1 Compare Functions56831.7.7 Data Format56831.7.8 Loop Mode57031.7.9 Interrupt57031.8 SSC Application Examples57131.8.1 Write Protection Registers57231.9 Synchronous Serial Controller (SSC) User Interface57331.9.1 SSC Control Register57431.9.2 SSC Clock Mode Register57531.9.3 SSC Receive Clock Mode Register57631.9.4 SSC Receive Frame Mode Register57831.9.5 SSC Transmit Clock Mode Register58031.9.6 SSC Transmit Frame Mode Register58231.9.7 SSC Receive Holding Register58431.9.8 SSC Transmit Holding Register58431.9.9 SSC Receive Synchronization Holding Register58531.9.10 SSC Transmit Synchronization Holding Register58531.9.11 SSC Receive Compare 0 Register58631.9.12 SSC Receive Compare 1 Register58631.9.13 SSC Status Register58731.9.14 SSC Interrupt Enable Register58931.9.15 SSC Interrupt Disable Register59131.9.16 SSC Interrupt Mask Register59331.9.17 SSC Write Protect Mode Register59531.9.18 SSC Write Protect Status Register59632. Serial Peripheral Interface (SPI)59732.1 Description59732.2 Embedded Characteristics59732.3 Block Diagram59832.4 Application Block Diagram59832.5 Signal Description59932.6 Product Dependencies59932.6.1 I/O Lines59932.6.2 Power Management59932.6.3 Interrupt60032.6.4 Peripheral DMA Controller (PDC)60032.7 Functional Description60032.7.1 Modes of Operation60032.7.2 Data Transfer60032.7.3 Master Mode Operations60232.7.3.1 Master Mode Block Diagram60332.7.3.2 Master Mode Flow Diagram60432.7.3.3 Clock Generation60632.7.3.4 Transfer Delays60632.7.3.5 Peripheral Selection60732.7.3.6 SPI Peripheral DMA Controller (PDC)60732.7.3.7 Peripheral Chip Select Decoding60832.7.3.8 Peripheral Deselection without PDC60932.7.3.9 Peripheral Deselection with PDC60932.7.3.10 Mode Fault Detection61132.7.4 SPI Slave Mode61132.7.5 Write Protected Registers61232.8 Serial Peripheral Interface (SPI) User Interface61332.8.1 SPI Control Register61432.8.2 SPI Mode Register61532.8.3 SPI Receive Data Register61732.8.4 SPI Transmit Data Register61832.8.5 SPI Status Register61932.8.6 SPI Interrupt Enable Register62132.8.7 SPI Interrupt Disable Register62232.8.8 SPI Interrupt Mask Register62332.8.9 SPI Chip Select Register62432.8.10 SPI Write Protection Mode Register62732.8.11 SPI Write Protection Status Register62833. Two-wire Interface (TWI)62933.1 Description62933.2 Embedded Characteristics62933.3 List of Abbreviations63033.4 Block Diagram63033.5 Application Block Diagram63133.5.1 I/O Lines Description63133.6 Product Dependencies63133.6.1 I/O Lines63133.6.2 Power Management63233.6.3 Interrupt63233.7 Functional Description63233.7.1 Transfer Format63233.7.2 Modes of Operation63333.8 Master Mode63333.8.1 Definition63333.8.2 Application Block Diagram63333.8.3 Programming Master Mode63333.8.4 Master Transmitter Mode63433.8.5 Master Receiver Mode63633.8.6 Internal Address63733.8.6.1 7-bit Slave Addressing63733.8.6.2 10-bit Slave Addressing63833.8.7 Using the Peripheral DMA Controller (PDC)63833.8.7.1 Data Transmit with the PDC63833.8.7.2 Data Receive with the PDC63933.8.8 SMBUS Quick Command (Master Mode Only)63933.8.9 Read-write Flowcharts63933.9 Multi-master Mode64633.9.1 Definition64633.9.2 Different Multi-master Modes64633.9.2.1 TWI as Master Only64633.9.2.2 TWI as Master or Slave64633.10 Slave Mode64933.10.1 Definition64933.10.2 Application Block Diagram64933.10.3 Programming Slave Mode64933.10.4 Receiving Data64933.10.4.1 Read Sequence64933.10.4.2 Write Sequence65033.10.4.3 Clock Synchronization Sequence65033.10.4.4 General Call65033.10.5 Data Transfer65033.10.5.1 Read Operation65033.10.5.2 Write Operation65133.10.5.3 General Call65133.10.5.4 Clock Synchronization65233.10.5.5 Reversal after a Repeated Start65433.10.6 Read Write Flowcharts65533.11 Two-wire Interface (TWI) User Interface65633.11.1 TWI Control Register65733.11.2 TWI Master Mode Register65933.11.3 TWI Slave Mode Register66033.11.4 TWI Internal Address Register66133.11.5 TWI Clock Waveform Generator Register66233.11.6 TWI Status Register66333.11.7 TWI Interrupt Enable Register66633.11.8 TWI Interrupt Disable Register66733.11.9 TWI Interrupt Mask Register66833.11.10 TWI Receive Holding Register66933.11.11 TWI Transmit Holding Register67034. Universal Asynchronous Receiver Transmitter (UART)67134.1 Description67134.2 Embedded Characteristics67134.3 Block Diagram67134.4 Product Dependencies67234.4.1 I/O Lines67234.4.2 Power Management67234.4.3 Interrupt Source67234.5 UART Operations67234.5.1 Baud Rate Generator67234.5.2 Receiver67334.5.2.1 Receiver Reset, Enable and Disable67334.5.2.2 Start Detection and Data Sampling67334.5.2.3 Receiver Ready67434.5.2.4 Receiver Overrun67434.5.2.5 Parity Error67434.5.2.6 Receiver Framing Error67534.5.3 Transmitter67534.5.3.1 Transmitter Reset, Enable and Disable67534.5.3.2 Transmit Format67534.5.3.3 Transmitter Control67634.5.4 Peripheral DMA Controller67634.5.5 Test Modes67734.6 Universal Asynchronous Receiver Transmitter (UART) User Interface67834.6.1 UART Control Register67934.6.2 UART Mode Register68034.6.3 UART Interrupt Enable Register68134.6.4 UART Interrupt Disable Register68234.6.5 UART Interrupt Mask Register68334.6.6 UART Status Register68434.6.7 UART Receiver Holding Register68634.6.8 UART Transmit Holding Register68734.6.9 UART Baud Rate Generator Register68835. Universal Synchronous Asynchronous Receiver Transmitter (USART)68935.1 Description68935.2 Embedded Characteristics68935.3 Block Diagram69035.4 Application Block Diagram69135.5 I/O Lines Description69135.6 Product Dependencies69235.6.1 I/O Lines69235.6.2 Power Management69235.6.3 Interrupt69335.7 Functional Description69335.7.1 Baud Rate Generator69435.7.1.1 Baud Rate in Asynchronous Mode69435.7.1.2 Fractional Baud Rate in Asynchronous Mode69535.7.1.3 Baud Rate in Synchronous Mode or SPI Mode69635.7.1.4 Baud Rate in ISO 7816 Mode69635.7.2 Receiver and Transmitter Control69835.7.3 Synchronous and Asynchronous Modes69835.7.3.1 Transmitter Operations69835.7.3.2 Manchester Encoder69935.7.3.3 Asynchronous Receiver70135.7.3.4 Manchester Decoder70235.7.3.5 Radio Interface: Manchester Encoded USART Application70435.7.3.6 Synchronous Receiver70535.7.3.7 Receiver Operations70635.7.3.8 Parity70635.7.3.9 Multidrop Mode70735.7.3.10 Transmitter Timeguard70835.7.3.11 Receiver Time-out70835.7.3.12 Framing Error71035.7.3.13 Transmit Break71035.7.3.14 Receive Break71135.7.3.15 Hardware Handshaking71135.7.4 ISO7816 Mode71235.7.4.1 ISO7816 Mode Overview71235.7.4.2 Protocol T = 071335.7.4.3 Protocol T = 171435.7.5 IrDA Mode71435.7.5.1 IrDA Modulation71535.7.5.2 IrDA Baud Rate71535.7.5.3 IrDA Demodulator71635.7.6 RS485 Mode71735.7.7 Modem Mode71835.7.8 SPI Mode71835.7.8.1 Modes of Operation71935.7.8.2 Baud Rate71935.7.8.3 Data Transfer72035.7.8.4 Receiver and Transmitter Control72135.7.8.5 Character Transmission72135.7.8.6 Character Reception72235.7.8.7 Receiver Timeout72235.7.9 Test Modes72235.7.9.1 Normal Mode72235.7.9.2 Automatic Echo Mode72235.7.9.3 Local Loopback Mode72235.7.9.4 Remote Loopback Mode72335.7.10 Write Protection Registers72335.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface72435.8.1 USART Control Register72535.8.2 USART Control Register (SPI_MODE)72735.8.3 USART Mode Register72935.8.4 USART Mode Register (SPI_MODE)73235.8.5 USART Interrupt Enable Register73435.8.6 USART Interrupt Enable Register (SPI_MODE)73635.8.7 USART Interrupt Disable Register73735.8.8 USART Interrupt Disable Register (SPI_MODE)73935.8.9 USART Interrupt Mask Register74035.8.10 USART Interrupt Mask Register (SPI_MODE)74235.8.11 USART Channel Status Register74335.8.12 USART Channel Status Register (SPI_MODE)74635.8.13 USART Receive Holding Register74735.8.14 USART Transmit Holding Register74835.8.15 USART Baud Rate Generator Register74935.8.16 USART Receiver Time-out Register75035.8.17 USART Transmitter Timeguard Register75135.8.18 USART FI DI RATIO Register75235.8.19 USART Number of Errors Register75335.8.20 USART IrDA FILTER Register75335.8.21 USART Manchester Configuration Register75435.8.22 USART Write Protect Mode Register75635.8.23 USART Write Protect Status Register75735.8.24 USART Version Register75836. Timer Counter (TC)75936.1 Description75936.2 Embedded Characteristics75936.3 Block Diagram76036.4 Pin Name List76136.5 Product Dependencies76136.5.1 I/O Lines76136.5.2 Power Management76136.5.3 Interrupt76236.5.4 Fault Output76236.6 Functional Description76236.6.1 TC Description76236.6.2 16-bit Counter76236.6.3 Clock Selection76236.6.4 Clock Control76436.6.5 TC Operating Modes76436.6.6 Trigger76536.6.7 Capture Operating Mode76536.6.8 Capture Registers A and B76536.6.9 Trigger Conditions76636.6.10 Waveform Operating Mode76836.6.11 Waveform Selection76836.6.11.1 WAVSEL = 0077036.6.11.2 WAVSEL = 1077136.6.11.3 WAVSEL = 0177236.6.11.4 WAVSEL = 1177336.6.12 External Event/Trigger Conditions77436.6.13 Output Controller77436.6.14 Quadrature Decoder Logic77536.6.14.1 Description77536.6.14.2 Input Pre-processing77636.6.14.3 Direction Status and Change Detection77936.6.14.4 Position and Rotation Measurement78036.6.14.5 Speed Measurement78136.6.15 2-bit Gray Up/Down Counter for Stepper Motor78136.6.16 Write Protection System78136.6.17 Fault Mode78236.7 Timer Counter (TC) User Interface78336.7.1 TC Channel Control Register78436.7.2 TC Channel Mode Register: Capture Mode78536.7.3 TC Channel Mode Register: Waveform Mode78736.7.4 TC Stepper Motor Mode Register79136.7.5 TC Counter Value Register79236.7.6 TC Register A79336.7.7 TC Register B79336.7.8 TC Register C79436.7.9 TC Status Register79536.7.10 TC Interrupt Enable Register79736.7.11 TC Interrupt Disable Register79836.7.12 TC Interrupt Mask Register79936.7.13 TC Block Control Register80036.7.14 TC Block Mode Register80136.7.15 TC QDEC Interrupt Enable Register80336.7.16 TC QDEC Interrupt Disable Register80436.7.17 TC QDEC Interrupt Mask Register80536.7.18 TC QDEC Interrupt Status Register80636.7.19 TC Fault Mode Register80736.7.20 TC Write Protect Mode Register80837. High Speed MultiMedia Card Interface (HSMCI)80937.1 Description80937.2 Embedded Characteristics80937.3 Block Diagram81037.4 Application Block Diagram81037.5 Pin Name List81137.6 Product Dependencies81137.6.1 I/O Lines81137.6.2 Power Management81137.6.3 Interrupt81137.7 Bus Topology81237.8 High Speed MultiMedia Card Operations81437.8.1 Command - Response Operation81437.8.2 Data Transfer Operation81737.8.3 Read Operation81737.8.4 Write Operation81937.9 SD/SDIO Card Operation82237.9.1 SDIO Data Transfer Type82237.9.2 SDIO Interrupts82237.10 CE-ATA Operation82237.10.1 Executing an ATA Polling Command82337.10.2 Executing an ATA Interrupt Command82337.10.3 Aborting an ATA Command82337.10.4 CE-ATA Error Recovery82337.11 HSMCI Boot Operation Mode82437.11.1 Boot Procedure, Processor Mode82437.12 HSMCI Transfer Done Timings82437.12.1 Definition82437.12.2 Read Access82437.12.3 Write Access82537.13 Write Protection Registers82537.14 High Speed MultiMedia Card Interface (HSMCI) User Interface82637.14.1 HSMCI Control Register82737.14.2 HSMCI Mode Register82837.14.3 HSMCI Data Timeout Register83037.14.4 HSMCI SDCard/SDIO Register83137.14.5 HSMCI Argument Register83237.14.6 HSMCI Command Register83337.14.7 HSMCI Block Register83537.14.8 HSMCI Completion Signal Timeout Register83637.14.9 HSMCI Response Register83737.14.10 HSMCI Receive Data Register83837.14.11 HSMCI Transmit Data Register83937.14.12 HSMCI Status Register84037.14.13 HSMCI Interrupt Enable Register84437.14.14 HSMCI Interrupt Disable Register84637.14.15 HSMCI Interrupt Mask Register84837.14.16 HSMCI Configuration Register85037.14.17 HSMCI Write Protect Mode Register85137.14.18 HSMCI Write Protect Status Register85238. Pulse Width Modulation Controller (PWM)85338.1 Description85338.2 Embedded Characteristics85338.3 Block Diagram85438.4 I/O Lines Description85438.5 Product Dependencies85538.5.1 I/O Lines85538.5.2 Power Management85638.5.3 Interrupt Sources85638.5.4 Fault Inputs85638.6 Functional Description85638.6.1 PWM Clock Generator85738.6.2 PWM Channel85838.6.2.1 Channel Block Diagram85838.6.2.2 Comparator85838.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor86138.6.2.4 Dead-Time Generator86238.6.2.5 Output Override86338.6.2.6 Fault Protection86438.6.2.7 Synchronous Channels86538.6.3 PWM Comparison Units87138.6.4 PWM Event Lines87338.6.5 PWM Controller Operations87338.6.5.1 Initialization87338.6.5.2 Source Clock Selection Criteria87438.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times87438.6.5.4 Changing the Synchronous Channels Update Period87638.6.5.5 Changing the Comparison Value and the Comparison Configuration87738.6.5.6 Interrupts87738.6.5.7 Write Protect Registers87838.7 Pulse Width Modulation Controller (PWM) Controller User Interface87938.7.1 PWM Clock Register88238.7.2 PWM Enable Register88338.7.3 PWM Disable Register88438.7.4 PWM Status Register88538.7.5 PWM Interrupt Enable Register 188638.7.6 PWM Interrupt Disable Register 188738.7.7 PWM Interrupt Mask Register 188838.7.8 PWM Interrupt Status Register 188938.7.9 PWM Sync Channels Mode Register89038.7.10 PWM Sync Channels Update Control Register89138.7.11 PWM Sync Channels Update Period Register89238.7.12 PWM Sync Channels Update Period Update Register89338.7.13 PWM Interrupt Enable Register 289438.7.14 PWM Interrupt Disable Register 289538.7.15 PWM Interrupt Mask Register 289638.7.16 PWM Interrupt Status Register 289738.7.17 PWM Output Override Value Register89838.7.18 PWM Output Selection Register89938.7.19 PWM Output Selection Set Register90038.7.20 PWM Output Selection Clear Register90138.7.21 PWM Output Selection Set Update Register90238.7.22 PWM Output Selection Clear Update Register90338.7.23 PWM Fault Mode Register90438.7.24 PWM Fault Status Register90538.7.25 PWM Fault Clear Register90638.7.26 PWM Fault Protection Value Register90738.7.27 PWM Fault Protection Enable Register90838.7.28 PWM Event Line x Register90938.7.29 PWM Stepper Motor Mode Register91038.7.30 PWM Write Protect Control Register91138.7.31 PWM Write Protect Status Register91338.7.32 PWM Comparison x Value Register91438.7.33 PWM Comparison x Value Update Register91538.7.34 PWM Comparison x Mode Register91638.7.35 PWM Comparison x Mode Update Register91738.7.36 PWM Channel Mode Register91838.7.37 PWM Channel Duty Cycle Register92038.7.38 PWM Channel Duty Cycle Update Register92138.7.39 PWM Channel Period Register92238.7.40 PWM Channel Period Update Register92338.7.41 PWM Channel Counter Register92438.7.42 PWM Channel Dead Time Register92538.7.43 PWM Channel Dead Time Update Register92639. USB Device Port (UDP)92739.1 Description92739.2 Embedded Characteristics92739.3 Block Diagram92839.3.1 Signal Description92839.4 Product Dependencies92939.4.1 I/O Lines92939.4.2 Power Management92939.4.3 Interrupt92939.5 Typical Connection93039.5.1 USB Device Transceiver93039.5.2 VBUS Monitoring93039.6 Functional Description93139.6.1 USB V2.0 Full-speed Introduction93139.6.1.1 USB V2.0 Full-speed Transfer Types93139.6.1.2 USB Bus Transactions93139.6.1.3 USB Transfer Event Definitions93239.6.2 Handling Transactions with USB V2.0 Device Peripheral93339.6.2.1 Setup Transaction93339.6.2.2 Data IN Transaction93439.6.2.3 Data OUT Transaction93739.6.2.4 Stall Handshake93939.6.2.5 Transmit Data Cancellation94039.6.3 Controlling Device States94139.6.3.1 Not Powered State94239.6.3.2 Entering Attached State94239.6.3.3 From Powered State to Default State94239.6.3.4 From Default State to Address State94239.6.3.5 From Address State to Configured State94239.6.3.6 Entering in Suspend State94239.6.3.7 Receiving a Host Resume94339.6.3.8 Sending a Device Remote Wake-up94339.7 USB Device Port (UDP) User Interface94439.7.1 UDP Frame Number Register94539.7.2 UDP Global State Register94639.7.3 UDP Function Address Register94739.7.4 UDP Interrupt Enable Register94839.7.5 UDP Interrupt Disable Register94939.7.6 UDP Interrupt Mask Register95039.7.7 UDP Interrupt Status Register95239.7.8 UDP Interrupt Clear Register95439.7.9 UDP Reset Endpoint Register95539.7.10 UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints)95639.7.11 UDP Endpoint Control and Status Register (Isochronous Endpoints)96139.7.12 UDP FIFO Data Register96539.7.13 UDP Transceiver Control Register96640. Analog Comparator Controller (ACC)96740.1 Description96740.2 Embedded Characteristics96740.3 Block Diagram96740.4 Pin Name List96840.5 Product Dependencies96840.5.1 I/O Lines96840.5.2 Power Management96840.5.3 Interrupt96840.5.4 Fault Output96840.6 Functional Description96940.6.1 ACC Description96940.6.2 Analog Settings96940.6.3 Write Protection System96940.6.4 Automatic Output Masking Period96940.6.5 Fault Mode96940.7 Analog Comparator Controller (ACC) User Interface97040.7.1 ACC Control Register97140.7.2 ACC Mode Register97240.7.3 ACC Interrupt Enable Register97440.7.4 ACC Interrupt Disable Register97540.7.5 ACC Interrupt Mask Register97640.7.6 ACC Interrupt Status Register97740.7.7 ACC Analog Control Register97840.7.8 ACC Write Protect Mode Register97940.7.9 ACC Write Protect Status Register98041. Analog-to-Digital Converter (ADC)98141.1 Description98141.2 Embedded Characteristics98141.3 Block Diagram98241.4 Signal Description98241.5 Product Dependencies98241.5.1 Power Management98241.5.2 Interrupt Sources98241.5.3 Analog Inputs98341.5.4 Temperature Sensor98341.5.5 I/O Lines98341.5.6 Timer Triggers98341.5.7 PWM Event Line98341.5.8 Fault Output98441.5.9 Conversion Performances98441.6 Functional Description98441.6.1 Analog-to-digital Conversion98441.6.2 Conversion Reference98541.6.3 Conversion Resolution98541.6.4 Conversion Results98541.6.5 Conversion Triggers98841.6.6 Sleep Mode and Conversion Sequencer98841.6.7 Comparison Window98941.6.8 Differential Inputs98941.6.9 Input Gain and Offset99041.6.10 ADC Timings99141.6.11 Automatic Calibration99241.6.12 Buffer Structure99241.6.13 Fault Output99241.6.14 Write Protected Registers99341.7 Analog-to-Digital Converter (ADC) User Interface99441.7.1 ADC Control Register99541.7.2 ADC Mode Register99641.7.3 ADC Channel Sequence 1 Register99941.7.4 ADC Channel Sequence 2 Register100041.7.5 ADC Channel Enable Register100141.7.6 ADC Channel Disable Register100241.7.7 ADC Channel Status Register100341.7.8 ADC Last Converted Data Register100341.7.9 ADC Interrupt Enable Register100441.7.10 ADC Interrupt Disable Register100541.7.11 ADC Interrupt Mask Register100641.7.12 ADC Interrupt Status Register100741.7.13 ADC Overrun Status Register100841.7.14 ADC Extended Mode Register100941.7.15 ADC Compare Window Register101041.7.16 ADC Channel Gain Register101141.7.17 ADC Channel Offset Register101241.7.18 ADC Channel Data Register101341.7.19 ADC Analog Control Register101441.7.20 ADC Write Protect Mode Register101541.7.21 ADC Write Protect Status Register101642. Digital-to-Analog Converter Controller (DACC)101742.1 Description101742.2 Embedded characteristics101742.3 Block Diagram101842.4 Signal Description101842.5 Product Dependencies101942.5.1 Power Management101942.5.2 Interrupt Sources101942.5.3 Conversion Performances101942.6 Functional Description102042.6.1 Digital-to-Analog Conversion102042.6.2 Conversion Results102042.6.3 Conversion Triggers102042.6.4 Conversion FIFO102042.6.5 Channel Selection102042.6.6 Sleep Mode102142.6.7 DACC Timings102142.6.8 Write Protection Registers102242.7 Digital-to-Analog Converter (DACC) User Interface102342.7.1 DACC Control Register102442.7.2 DACC Mode Register102542.7.3 DACC Channel Enable Register102842.7.4 DACC Channel Disable Register102942.7.5 DACC Channel Status Register103042.7.6 DACC Conversion Data Register103142.7.7 DACC Interrupt Enable Register103242.7.8 DACC Interrupt Disable Register103342.7.9 DACC Interrupt Mask Register103442.7.10 DACC Interrupt Status Register103542.7.11 DACC Analog Current Register103642.7.12 DACC Write Protect Mode Register103742.7.13 DACC Write Protect Status Register103843. SAM4S Electrical Characteristics103943.1 Absolute Maximum Ratings103943.2 DC Characteristics104043.3 Power Consumption104643.3.1 Backup Mode Current Consumption104643.3.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled104643.3.1.2 Configuration B: 32768kHz Crystal Oscillator Enabled104643.3.2 Sleep and Wait Mode Current Consumption104743.3.2.1 Sleep Mode104743.3.2.2 Wait Mode105143.3.3 Active Mode Power Consumption105243.3.3.1 SAM4S16/S8 Active Power Consumption105343.3.3.2 SAM4SD32/SD16/SA16 Active Power Consumption105543.3.4 Peripheral Power Consumption in Active Mode105643.4 Oscillator Characteristics105743.4.1 32 kHz RC Oscillator Characteristics105743.4.2 4/8/12 MHz RC Oscillators Characteristics105743.4.3 32.768 kHz Crystal Oscillator Characteristics105843.4.4 32.768 kHz Crystal Characteristics105843.4.5 3 to 20 MHz Crystal Oscillator Characteristics105943.4.6 3 to 20 MHz Crystal Characteristics106043.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode106043.4.8 Crystal Oscillator Design Considerations Information106143.4.8.1 Choosing a Crystal106143.4.8.2 Printed Circuit Board (PCB)106143.5 PLLA, PLLB Characteristics106243.6 USB Transceiver Characteristics106343.6.1 Typical Connection106343.6.2 Electrical Parameters106343.6.3 Switching Characteristics106443.7 12-Bit ADC Characteristics106543.7.1 Static Performance Characteristics106643.7.1.1 Track and Hold Time versus Source Output Impedance106843.8 12-Bit DAC Characteristics107043.9 Analog Comparator Characteristics107243.10 Temperature Sensor107243.11 AC Characteristics107343.11.1 Master Clock Characteristics107343.11.2 I/O Characteristics107343.11.3 SPI Characteristics107443.11.3.1 Maximum SPI Frequency107543.11.3.2 SPI Timings107643.11.4 HSMCI Timings107643.11.5 SSC Timings107743.11.6 SMC Timings108143.11.6.1 Read Timings108143.11.6.2 Write Timings108243.11.7 USART in SPI Mode Timings108543.11.7.1 USART SPI TImings108743.11.8 Two-wire Serial Interface Characteristics108843.11.9 Embedded Flash Characteristics108944. SAM4S Mechanical Characteristics109044.1 Soldering Profile109944.2 Packaging Resources109945. Ordering Information110146. Errata on SAM4S Devices110546.1 Marking110546.2 Errata SAM4SD32/SD16/SA16/S16/S8 Rev A Parts110546.2.1 Flash Controller110546.2.1.1 EFC: Flash Buffer not Cleared110546.2.1.2 EFC: Code Loop Optimization Cannot Be Disabled110546.2.2 Flash110646.2.2.1 Flash: Read Error after a GPNVM or Lock Bit Writing110646.2.3 Watchdog110646.2.3.1 Watchdog Not Stopped in Wait Mode110646.2.4 Brownout Detector110646.2.4.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected1106Revision History1107Table of Contents1117Tamaño: 4 MBPáginas: 1125Language: EnglishManuales abiertas
