Manual De UsuarioTabla de contenidosTable of Contents31 Introduction32 Basic Architecture33 Instruction Formats44 Instruction Descriptions45 System Architecture and Programming Implications76 Common PALcode Architecture77 Console Subsystem Overview88 Input/Output Overview89 OpenVMS Alpha810 Digital UNIX811 Windows NT Alpha8A Software Considerations8B IEEE Floating-Point Conformance9C Instruction Summary9D Registered System and Processor Identifiers9E Waivers and Implementation-Dependent Functionality9Figures11Tables12Preface15Introduction171.1 The Alpha Approach to RISC Architecture171.2 Data Format Overview191.3 Instruction Format Overview201.4 Instruction Overview201.5 Instruction Set Characteristics221.6 Terminology and Conventions221.6.1 Numbering231.6.2 Security Holes231.6.3 UNPREDICTABLE and UNDEFINED231.6.4 Ranges and Extents241.6.5 ALIGNED and UNALIGNED241.6.6 Must Be Zero (MBZ)251.6.7 Read As Zero (RAZ)251.6.8 Should Be Zero (SBZ)251.6.9 Ignore (IGN)251.6.10 Implementation Dependent (IMP)251.6.11 Illustration Conventions251.6.12 Macro Code Example Conventions25Basic Architecture272.1 Addressing272.2 Data Types272.2.1 Byte272.2.2 Word272.2.3 Longword282.2.4 Quadword282.2.5 VAX Floating-Point Formats292.2.5.1 F_floating292.2.5.2 G_floating302.2.5.3 D_floating312.2.6 IEEE Floating-Point Formats322.2.6.1 S_Floating332.2.6.2 T_floating342.2.6.3 X_Floating352.2.7 Longword Integer Format in Floating-Point Unit372.2.8 Quadword Integer Format in Floating-Point Unit382.2.9 Data Types with No Hardware Support382.3 Big-Endian Addressing Support39Instruction Formats413.1 Alpha Registers413.1.1 Program Counter413.1.2 Integer Registers413.1.3 Floating-Point Registers423.1.4 Lock Registers423.1.5 Processor Cycle Counter (PCC) Register433.1.6 Optional Registers433.1.6.1 Memory Prefetch Registers433.1.6.2 VAX Compatibility Register433.2 Notation433.2.1 Operand Notation443.2.2 Instruction Operand Notation453.2.2.1 Operand Name Notation453.2.2.2 Operand Access Type Notation453.2.2.3 Operand Data Type Notation463.2.3 Operators463.2.4 Notation Conventions503.3 Instruction Formats503.3.1 Memory Instruction Format513.3.1.1 Memory Format Instructions with a Function Code513.3.1.2 Memory Format Jump Instructions523.3.2 Branch Instruction Format523.3.3 Operate Instruction Format523.3.4 Floating-Point Operate Instruction Format533.3.4.1 Floating-Point Convert Instructions543.3.4.2 Floating-Point/Integer Register Moves543.3.5 PALcode Instruction Format54Instruction Descriptions574.1 Instruction Set Overview574.1.1 Subsetting Rules584.1.2 Floating-Point Subsets584.1.3 Software Emulation Rules594.1.4 Opcode Qualifiers594.2 Memory Integer Load/Store Instructions604.2.1 Load Address614.2.2 Load Memory Data into Integer Register624.2.3 Load Unaligned Memory Data into Integer Register644.2.4 Load Memory Data into Integer Register Locked654.2.5 Store Integer Register Data into Memory Conditional684.2.6 Store Integer Register Data into Memory714.2.7 Store Unaligned Integer Register Data into Memory734.3 Control Instructions744.3.1 Conditional Branch764.3.2 Unconditional Branch774.3.3 Jumps784.4 Integer Arithmetic Instructions804.4.1 Longword Add814.4.2 Scaled Longword Add824.4.3 Quadword Add834.4.4 Scaled Quadword Add844.4.5 Integer Signed Compare854.4.6 Integer Unsigned Compare864.4.7 Count Leading Zero874.4.8 Count Population884.4.9 Count Trailing Zero894.4.10 Longword Multiply904.4.11 Quadword Multiply914.4.12 Unsigned Quadword Multiply High924.4.13 Longword Subtract934.4.14 Scaled Longword Subtract944.4.15 Quadword Subtract954.4.16 Scaled Quadword Subtract964.5 Logical and Shift Instructions974.5.1 Logical Functions984.5.2 Conditional Move Integer994.5.3 Shift Logical1014.5.4 Shift Arithmetic1024.6 Byte Manipulation Instructions1034.6.1 Compare Byte1054.6.2 Extract Byte1074.6.3 Byte Insert1114.6.4 Byte Mask1134.6.5 Sign Extend1164.6.6 Zero Bytes1174.7 Floating-Point Instructions1184.7.1 Single-Precision Operations1184.7.2 Subsets and Faults1184.7.3 Definitions1194.7.4 Encodings1214.7.5 Rounding Modes1224.7.6 Computational Models1234.7.6.1 VAX-Format Arithmetic with Precise Exceptions1234.7.6.2 High-Performance VAX-Format Arithmetic1244.7.6.3 IEEE-Compliant Arithmetic1244.7.6.4 IEEE-Compliant Arithmetic Without Inexact Exception1244.7.6.5 High-Performance IEEE-Format Arithmetic1254.7.7 Trapping Modes1254.7.7.1 VAX Trapping Modes1254.7.7.2 IEEE Trapping Modes1274.7.7.3 Arithmetic Trap Completion1294.7.7.3.1 Trap Shadow Rules1294.7.7.3.2 Trap Shadow Length Rules1304.7.7.4 Invalid Operation (INV) Arithmetic Trap1324.7.7.5 Division by Zero (DZE) Arithmetic Trap1334.7.7.6 Overflow (OVF) Arithmetic Trap1334.7.7.7 Underflow (UNF) Arithmetic Trap1344.7.7.8 Inexact Result (INE) Arithmetic Trap1344.7.7.9 Integer Overflow (IOV) Arithmetic Trap1344.7.7.10 IEEE Floating-Point Trap Disable Bits1344.7.7.11 IEEE Denormal Control Bits1354.7.8 Floating-Point Control Register (FPCR)1354.7.8.1 Accessing the FPCR1384.7.8.2 Default Values of the FPCR1394.7.8.3 Saving and Restoring the FPCR1394.7.9 Floating-Point Instruction Function Field Format1404.7.10 IEEE Standard1444.7.10.1 Conversion of NaN and Infinity Values1444.7.10.2 Copying NaN Values1454.7.10.3 Generating NaN Values1454.7.10.4 Propagating NaN Values1454.8 Memory Format Floating-Point Instructions1464.8.1 Load F_floating1474.8.2 Load G_floating1484.8.3 Load S_floating1494.8.4 Load T_floating1504.8.5 Store F_floating1514.8.6 Store G_floating1524.8.7 Store S_floating1534.8.8 Store T_floating1544.9 Branch Format Floating-Point Instructions1554.9.1 Conditional Branch1564.10 Floating-Point Operate Format Instructions1584.10.1 Copy Sign1614.10.2 Convert Integer to Integer1624.10.3 Floating-Point Conditional Move1634.10.4 Move from/to Floating-Point Control Register1654.10.5 VAX Floating Add1664.10.6 IEEE Floating Add1674.10.7 VAX Floating Compare1684.10.8 IEEE Floating Compare1694.10.9 Convert VAX Floating to Integer1704.10.10 Convert Integer to VAX Floating1714.10.11 Convert VAX Floating to VAX Floating1724.10.12 Convert IEEE Floating to Integer1734.10.13 Convert Integer to IEEE Floating1744.10.14 Convert IEEE S_Floating to IEEE T_Floating1754.10.15 Convert IEEE T_Floating to IEEE S_Floating1764.10.16 VAX Floating Divide1774.10.17 IEEE Floating Divide1784.10.18 Floating-Point Register to Integer Register Move1794.10.19 Integer Register to Floating-Point Register Move1804.10.20 VAX Floating Multiply1824.10.21 IEEE Floating Multiply1834.10.22 VAX Floating Square Root1844.10.23 IEEE Floating Square Root1854.10.24 VAX Floating Subtract1864.10.25 IEEE Floating Subtract1874.11 Miscellaneous Instructions1884.11.1 Architecture Mask1894.11.2 Call Privileged Architecture Library1914.11.3 Evict Data Cache Block1924.11.4 Exception Barrier1944.11.5 Prefetch Data1954.11.6 Implementation Version1974.11.7 Memory Barrier1984.11.8 Read Processor Cycle Counter1994.11.9 Trap Barrier2004.11.10 Write Hint2014.11.11 Write Memory Barrier2034.12 VAX Compatibility Instructions2054.12.1 VAX Compatibility Instructions2064.13 Multimedia (Graphics and Video) Support2074.13.1 Byte and Word Minimum and Maximum2084.13.2 Pixel Error2104.13.3 Pack Bytes2114.13.4 Unpack Bytes212System Architecture and Programming Implications2135.1 Introduction2135.2 Physical Address Space Characteristics2135.2.1 Coherency of Memory Access2135.2.2 Granularity of Memory Access2145.2.3 Width of Memory Access2155.2.4 Memory-Like and Non-Memory-Like Behavior2155.3 Translation Buffers and Virtual Caches2165.4 Caches and Write Buffers2165.5 Data Sharing2185.5.1 Atomic Change of a Single Datum2185.5.2 Atomic Update of a Single Datum2185.5.3 Atomic Update of Data Structures2195.5.4 Ordering Considerations for Shared Data Structures2215.6 Read/Write Ordering2225.6.1 Alpha Shared Memory Model2225.6.1.1 Architectural Definition of Processor Issue Sequence2245.6.1.2 Definition of Before and After2245.6.1.3 Definition of Processor Issue Constraints2245.6.1.4 Definition of Location Access Constraints2265.6.1.5 Definition of Visibility2265.6.1.6 Definition of Storage2265.6.1.7 Definition of Dependence Constraint2275.6.1.8 Definition of Load-Locked and Store-Conditional2285.6.1.9 Timeliness2295.6.2 Litmus Tests2295.6.2.1 Litmus Test 1 (Impossible Sequence)2295.6.2.2 Litmus Test 2 (Impossible Sequence)2305.6.2.3 Litmus Test 3 (Impossible Sequence)2305.6.2.4 Litmus Test 4 (Sequence Okay)2315.6.2.5 Litmus Test 5 (Sequence Okay)2315.6.2.6 Litmus Test 6 (Sequence Okay)2315.6.2.7 Litmus Test 7 (Impossible Sequence)2325.6.2.8 Litmus Test 8 (Impossible Sequence)2325.6.2.9 Litmus Test 9 (Impossible Sequence)2335.6.2.10 Litmus Test 10 (Sequence Okay)2335.6.2.11 Litmus Test 11 (Impossible Sequence)2335.6.3 Implied Barriers2345.6.4 Implications for Software2345.6.4.1 Single Processor Data Stream2345.6.4.2 Single Processor Instruction Stream2345.6.4.3 Multiprocessor Data Stream (Including Single Processor with DMA I/O)2345.6.4.4 Multiprocessor Instruction Stream (Including Single Processor with DMA I/O)2355.6.4.5 Multiprocessor Context Switch2365.6.4.6 Multiprocessor Send/Receive Interrupt2385.6.4.7 Implications for Memory Mapped I/O2395.6.4.8 Multiple Processors Writing to a Single I/O Device2405.6.5 Implications for Hardware2415.7 Arithmetic Traps242Common PALcode Architecture2436.1 PALcode2436.2 PALcode Instructions and Functions2436.3 PALcode Environment2446.4 Special Functions Required for PALcode2446.5 PALcode Effects on System Code2456.6 PALcode Replacement2456.7 Required PALcode Instructions2466.7.1 Drain Aborts2486.7.2 Halt2496.7.3 Instruction Memory Barrier250Console Subsystem Overview251Input/Output Overview253OpenVMS Alpha2559.1 Unprivileged OpenVMS Alpha PALcode2559.2 Privileged OpenVMS Alpha Palcode262Digital UNIX26510.1 Unprivileged Digital UNIX PALcode26510.2 Privileged Digital UNIX PALcode266Windows NT Alpha26911.1 Unprivileged Windows NT Alpha PALcode26911.2 Privileged Windows NT Alpha PALcode270Software Considerations275A.1 Hardware-Software Compact275A.2 Instruction-Stream Considerations276A.2.1 Instruction Alignment276A.2.2 Branch Prediction and Minimizing Branch-Taken — Factor of 3276A.2.3 Improving I-Stream Density — Factor of 3278A.2.4 Instruction Scheduling — Factor of 3278A.3 Data-Stream Considerations278A.3.1 Data Alignment — Factor of 10278A.3.2 Shared Data in Multiple Processors — Factor of 3279A.3.3 Avoiding Cache/TB Conflicts — Factor of 1280A.3.4 Sequential Read/Write — Factor of 1282A.3.5 Prefetching — Factor of 3282A.4 Code Sequences283A.4.1 Aligned Byte/Word (Within Register) Memory Accesses283A.4.2 Division284A.4.3 Byte Swap285A.4.4 Stylized Code Forms285A.4.4.1 NOP285A.4.4.2 Clear a Register286A.4.4.3 Load Literal286A.4.4.4 Register-to-Register Move287A.4.4.5 Negate287A.4.4.6 NOT287A.4.4.7 Booleans287A.4.5 Exceptions and Trap Barriers288A.4.6 Pseudo-Operations (Stylized Code Forms)288A.5 Timing Considerations: Atomic Sequences290IEEE Floating-Point Conformance291B.1 Alpha Choices for IEEE Options291B.2 Alpha Support for OS Completion Handlers293B.2.1 IEEE Floating-Point Control (FP_C) Quadword294B.3 Mapping to IEEE Standard296Instruction Summary303C.1 Common Architecture Instruction Summary303C.2 IEEE Floating-Point Instructions308C.3 VAX Floating-Point Instructions309C.4 Independent Floating-Point Instructions310C.5 Opcode Summary310C.6 Common Architecture Opcodes in Numerical Order312C.7 OpenVMS Alpha PALcode Instruction Summary316C.8 DIGITAL UNIX PALcode Instruction Summary318C.9 Windows NT Alpha Instruction Summary319C.10 PALcode Opcodes in Numerical Order320C.11 Required PALcode Opcodes322C.12 Opcodes Reserved to PALcode322C.13 Opcodes Reserved to Compaq323C.14 Unused Function Code Behavior323C.15 ASCII Character Set324Registered System and Processor Identifiers325D.1 Processor Type Assignments325D.2 PALcode Variation Assignments326D.3 Architecture Mask and Implementation Values327Waivers and Implementation-Dependent Functionality329E.1 Waivers329E.1.1 DECchip 21064, DECchip 21066, and DECchip 21068 IEEE Divide Instruction Violation329E.1.2 DECchip 21064, DECchip 21066, and DECchip 21068 Write Buffer Violation330E.1.3 DECchip 21264 LDx_L/STx_C with WH64 Violation330E.2 Implementation-Specific Functionality331E.2.1 DECchip 21064/21066/21068 Performance Monitoring331E.2.1.1 DECchip 21064/21066/21068 Performance Monitor Interrupt Mechanism332E.2.1.2 Functions and Arguments for the DECchip 21064/21066/21068333E.2.2 DECchip 21164/21164PC Performance Monitoring337E.2.2.1 Performance Monitor Interrupt Mechanism337E.2.2.2 Windows NT Alpha Functions and Argument338E.2.2.3 OpenVMS Alpha and DIGITAL UNIX Functions and Arguments340E.2.3 21264 Performance Monitoring351E.2.3.1 Performance Monitor Interrupt Mechanism351E.2.3.2 Windows NT Alpha Functions and Argument352E.2.3.3 OpenVMS Alpha and DIGITAL UNIX Functions and Arguments353Index359A359B360C360D361E362F362G363H363I364J365L365M366N367O367P367Q368R368S368T369U370V370W370X370Y371Z371Tamaño: 5 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