Manual De UsuarioTabla de contenidosSCOPE1USER DEFINITION1MANUAL ORGANIZATION1TERMINOLOGY AND CONVENTIONS2REFERENCE3DESCRIPTION4INTRODUCTION4KEY FEATURES4STANDARDS AND REGULATIONS5HARDWARE REQUIREMENTS5SPECIFICATIONS6SPECIFICATION SUMMARY6PHYSICAL SPECIFICATIONS7LOGICAL CONFIGURATIONS7PERFORMANCE SPECIFICATIONS8POWER REQUIREMENTS9ENVIRONMENTAL SPECIFICATIONS10RELIABILITY SPECIFICATIONS11INSTALLATION12SPACE REQUIREMENTS12UNPACKING INSTRUCTIONS13MOUNTING13Orientation13Clearance15Ventilation16CABLE CONNECTORS16DC Power Connector16AT-Bus Interface Connector16JUMPER BLOCK CONFIGURATIONS18DRIVE INSTALLATION20SYSTEM STARTUP PROCEDURE21Drive Installation to Access the Full Capacity Using 32GB Clip22DISK DRIVE OPERATION23HEAD / DISK ASSEMBLY (HDA)23Base Casting Assembly23DC Spindle Motor Assembly23Disk Stack Assembly25Head Stack Assembly25Voice Coil Motor and Actuator Latch Assemblies25Air Filtration System25DRIVE ELECTRONICS26Digital Signal Process and Interface Controller26AT Disk Controller26The Host Interface Control Block28The Buffer Control Block29The Disk Control Block29The Disk ECC Control Block31Frequency Synthesizer31Power Management31Read/Write IC31Time Base Generator32Automatic Gain Control32Asymmetry Correction Circuitry (ASC)32Analog Anti-Aliasing Low Pass Filter32Analog to Digital Converter (ADC) and FIR32SERVO SYSTEM34READ AND WRITE OPERATIONS34The Read Channel34The Write Channel35FIRMWARE FEATURES35Read Caching35Write Caching36Defect Management37Automatic Defect Allocation37Multi-burst ECC Correction37SMART37AAM37AT INTERFACE AND ATA COMMANDS39INTRODUCTION39PHYSICAL INTERFACE39Signal Conventions39Signal Summary39Signal Descriptions40CS1FX- (Drive Chip Select 0)40CS3FX- (Drive Chip Select 1)40DA0-2 (Drive Address Bus)40DASP- (Drive Active/Slave Present)40DD0-DD15 (Drive Data Bus)40DIOR- (Drive I/O Read)40DIOW- (Drive I/O Write)40DMACK- (DMA Acknowledge)41DMARQ (DMA Request)41INTRQ (Drive Interrupt)41IOCS16- (Drive 16-bit I/O)41IORDY (I/O Channel Ready)42PDIAG- (Passed Diagnostics)42RESET- (Drive Reset)42LOGICAL INTERFACE46General46Bit Conventions46Environment46I/O Register - Address48Control Block Register Descriptions49Alternate Status Register (3F6h)49Drive Address Register (3F7h)49Device Control Register (3F6h)49Command Block Register Descriptions50Data Register (1F0h)50Features Register (1F1h)50Sector Number Register (1F3h)50Error Register (1F1h)50Sector Count Register (1F2h)51Cylinder High Register (1F5h)51Cylinder Low Register (1F4h)51Command Register (1F7h)51Drive/Head Register (1F6h)51Status Register (1F7h)52AT COMMAND REGISTER DESCRIPTIONS53Check Power Mode (98h, E5h)56Download Micro Code (92h)56Execute Device Diagnostics (90h)56Flush Cache (E7h)57Format Track (50h)57Identify Device (ECh)57Idle (97h,E3h)62Idle Immediate (95h,E1h)62Initialize Device Parameters (91h)62Read Buffer (E4h)63Read DMA (C8h:with retry, C9h:without retry)63Read Long (22h:with retry, 23h: without retry)63Read Multiple Command (C4h)64Read Native Max Address (F8h)65Read Sector(s) (20h:with retry, 21h:without retry)65Read Verify Sector(s) (40h:with retry, 41h:without retry)66Recalibrate (1xh)66Seek (7xh)66Set Features (EFh)67Set Max Address (F9h)69Set Multiple Mode (C6h)70Sleep (99h, E6h)70Standby (96h,E2h)71SMART (B0h)71Smart disable operation (D9h)71Smart enable/disable attribute autosave (D2h)72Smart enable operations (D8h)72Smart execute off-line immediate (D4h)72Smart read data (D0h)73SMART read log sector (D5h)75SMART return status (DAh)75SMART save attribution value (D3h)75SMART write log sector (D6h)756.4.25 Standby (96h, E2h)766.4.26 Standby Immediate (94h, E0h)766.4.27 Write Buffer (E8h)766.4.28 Write Long (32h:with retry, 33h:without retry)766.4.29 Write DMA (CAh)766.4.30 Write Multiple Command (C5h)776.4.31 Write Sector(s) (30h:with retry, 31h:without retry)77PROGRAMMING REQUIREMENTS79Reset Response79Error Posting79Power Conditions81Sleep mode81Standby mode81Idle mode81Normal mode82PROTOCOL OVERVIEW83PIO Data in Commands83PIO Read Command84PIO Read Aborted Command84PIO Data Out Commands84PIO Write Command85PIO Write Aborted Command85Non-Data Commands86DMA Data Transfer Commands87Normal DMA transfer88Aborted DMA transfer88Aborted DMA Command88TIMING89Register transfers89PIO data transfers91Multiword DMA data transfer94Ultra DMA data transfer96Initiating an Ultra DMA data in burst96Ultra DMA data burst timing requirements97Sustained Ultra DMA data in burst98Host pausing an Ultra DMA data in burst99Device terminating an Ultra DMA data in burst100Host terminating an Ultra DMA data in burst101Initiating an Ultra DMA data out burst102Sustained Ultra DMA data out burst103Device pausing an Ultra DMA data out burst104Host terminating an Ultra DMA data out burst105Device terminating an Ultra DMA data out burst106MAINTENANCE107GENERAL INFORMATION107MAINTENANCE PRECAUTIONS107SERVICE AND REPAIR107Table 3-1 Specifications6Table 3-2 Physical Specifications7Table 3-3 Logical Configurations7Table 3-4 Performance Specifications8Table 3-5 Power Requirements9Table 3-6 Environmental Specifications10Table 3-6 Environmental Specifications (continued)11Table 3-7 Reliability Specifications11Table 4-1 Power Connector Pin Assignment16Table 4-2 Logical Drive Parameters21Table 6-1 AT-Bus Interface Signals43Table 6-2 Interface Signals Description45Table 6-3 I/O Port Function/Selection Address48Table 6-4 Command Codes and Parameters54Table 6-5 Diagnostic Codes57Table 6-6 IDENTIFY DEVICE information58Table 6-7 Automatic Standby Timer Periods62Table 6-8 Set Feature Register Definitions67Table 6-9 Transfer mode values67Table 6-10 SMART Feature register values71Table 6-11 Device SMART data structure73Table 6-12 Off-line data collection status values74Table 6-13 Command Errors80Table 6-14 Power Saving Mode81Table 6-15 Power Conditions82Table 6-16 Register transfer to/from device91Table 6-17 PIO data transfer to/from device93Table 6-18 Multiword DMA data transfer95Table 6-19 Ultra DMA data burst timing requirements97Figure 4-1 Mechanical Dimension12Figure 4-2 Mounting Dimensions (in Millimeters)14Figure 4-3 Mounting-Screw Clearance15Figure 4-4 DC Power Connector, Configuration Jumper Block & AT-Bus Interface Connector (JHST)17Figure 4-5 Jumper Pin Locations on the Drive PCBA19Figure 4-6 Options for Jumper Block Configuration19Figure 4-7 DC Power Connector and AT-Bus Interface Cable Connections20Figure 5-1 Exploded Mechanical View24Figure 5-2 SID2001 AT Controller Block Diagram27Figure 5-3 Read/Write 88C520033Figure 6-1 Register transfer to/from device90Figure 6-2 PIO data transfer to/from device92Figure 6-3 Multiword DMA data transfer94Figure 6-4 Initiating an Ultra DMA data in burst96Figure 6-5 Sustained Ultra DMA data in burst98Figure 6-6 Host pausing an Ultra DMA data in burst99Figure 6-7 Device terminating an Ultra DMA data in burst100Figure 6-8 Host terminating an Ultra DMA data in burst101Figure 6-9 Initiating an Ultra DMA data out burst102Figure 6-10 Sustained Ultra DMA data out burst103Figure 6-11 Device pausing an Ultra DMA data out burst104Figure 6-12 Host terminating an Ultra DMA data out burst105Figure 6-13 Device terminating an Ultra DMA data out burst106Tamaño: 2 MBPáginas: 115Language: EnglishManuales abiertas