Hitachi HDS721075CLA632 Manuel D’Utilisation
Hitachi hard disk drive specifications
72
9.12 48-bit Address Feature Set
The 48-bit Address feature set allows devices with capacities up to 281,474,976,710,655 sectors. This allows
device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred
by a single command are increased by increasing the allowable sector count to 16 bits.
device capacity up to 144,115,188,075,855,360 bytes. In addition, the number of sectors that may be transferred
by a single command are increased by increasing the allowable sector count to 16 bits.
Commands unique to the 48-bit Address feature set are:
Flush Cache Ext
Read DMA Ext
Read FPDMA Queued
Read Multiple Ext
Read Native Max Address Ext
Read Sector(s) Ext
Read Verify Sector(s) Ext
Set Max Address Ext
Write DMA Ext
Write DMA FUA Ext
Write FPDMA Queued
Write Multiple Ext
Write Multiple FUA Ext
Write Sector(s) Ext
Write Uncorrectable Ext
The 48-bit Address feature set operates in LBA addressing only. Devices also implement commands using
28-bit addressing, and 28-bit and 48-bit commands may be intermixed.
28-bit addressing, and 28-bit and 48-bit commands may be intermixed.
In a device, the Features, the Sector Count, the Sector Number, the Cylinder High, and the Cylinder Low
registers are a two-byte-deep FIFO. Each time one of these registers is written, the new content written is placed
into the "most recently written" location and the previous content is moved to "previous content" location.
registers are a two-byte-deep FIFO. Each time one of these registers is written, the new content written is placed
into the "most recently written" location and the previous content is moved to "previous content" location.
The host may read the "previous content" of the Features, the Sector Count, the Sector Number, the Cylinder
High, and the Cylinder Low registers by first setting the High Order Bit (HOB, bit 7) of the Device control register
to one and then reading the desired register. If HOB in the Device Control register is cleared to zero, the host
reads the "most recently written" content when the register is read. A write to any Command Block register shall
cause the device to clear the HOB bit to zero in the Device Control register. The "most recently written" content
always gets written by a register write regardless of the state of HOB in the Device Control register.
High, and the Cylinder Low registers by first setting the High Order Bit (HOB, bit 7) of the Device control register
to one and then reading the desired register. If HOB in the Device Control register is cleared to zero, the host
reads the "most recently written" content when the register is read. A write to any Command Block register shall
cause the device to clear the HOB bit to zero in the Device Control register. The "most recently written" content
always gets written by a register write regardless of the state of HOB in the Device Control register.
Support of the 48-bit Address feature set is indicated in the Identify Device response bit 10 word 83. In addition,
the maximum user LBA address accessible by 48-bit addressable commands is contained in Identify Device
response words 100 through 103.
the maximum user LBA address accessible by 48-bit addressable commands is contained in Identify Device
response words 100 through 103.
When the 48-bit Address feature set is implemented, the native maximum address is the value returned by a
Read Native Max Address Ext command. If the native maximum address is equal to or less than 268,435,455, a
Read Native Max Address shall return the native maximum address. If the native maximum address is greater
than 268,435,455, a Read Native Max Address shall return a value of 268,435,455.
Read Native Max Address Ext command. If the native maximum address is equal to or less than 268,435,455, a
Read Native Max Address shall return the native maximum address. If the native maximum address is greater
than 268,435,455, a Read Native Max Address shall return a value of 268,435,455.