Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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9.5.5. DACDATA
Palette Data Register
I/O (and Memory Offset) Address: 3C9h
Default: Undefined
Attributes: Read/Write
Default: Undefined
Attributes: Read/Write
Bit Description
7:0
Palette Data. This byte-wide data port provides read or write access to the three bytes of data of each
color data position selected using the Palette Read Index Register (DACRX) or the Palette Write Index
Register (DACWX).
color data position selected using the Palette Read Index Register (DACRX) or the Palette Write Index
Register (DACWX).
The three bytes in each color data position are read or written in three successive read or write
operations. The first byte read or written specifies the intensity of the red component of the color
specified in the selected color data position. The second byte is for the green component, and the third
byte is for the blue component. When writing data to a color data position, all three bytes must be
written before the hardware will actually update the three bytes of the selected color data position.
operations. The first byte read or written specifies the intensity of the red component of the color
specified in the selected color data position. The second byte is for the green component, and the third
byte is for the blue component. When writing data to a color data position, all three bytes must be
written before the hardware will actually update the three bytes of the selected color data position.
When reading or writing to a color data position, ensure that neither the Palette Read Index Register
(DACRX) or the Palette Write Index Register (DACWX) are written to before all three bytes are read or
written. A write to either of these two registers causes the circuitry that automatically cycles through
providing access to the bytes for red, green and blue components to be reset such that the byte for the
red component is the one that will be accessed by the next read or write operation via this register.
(DACRX) or the Palette Write Index Register (DACWX) are written to before all three bytes are read or
written. A write to either of these two registers causes the circuitry that automatically cycles through
providing access to the bytes for red, green and blue components to be reset such that the byte for the
red component is the one that will be accessed by the next read or write operation via this register.
9.6.
CRT Controller Register
The CRT controller registers are accessed by writing the index of the desired register into the CRT
Controller Index Register at I/O address 3B4h or 3D4h, depending on whether the graphics system is
configured for MDA or CGA emulation. The desired register is then accessed through the data port for
the CRT controller registers located at I/O address 3B5h or 3D5h, again depending upon the choice of
MDA or CGA emulation as per MSR[0]. For memory mapped accesses, the Index register is at 3B4h
(MDA mode) or 3D3h (CGA mode) and the data port is accessed at 3B5h (MDA mode) or 3D5h (CGA
mode).
Controller Index Register at I/O address 3B4h or 3D4h, depending on whether the graphics system is
configured for MDA or CGA emulation. The desired register is then accessed through the data port for
the CRT controller registers located at I/O address 3B5h or 3D5h, again depending upon the choice of
MDA or CGA emulation as per MSR[0]. For memory mapped accesses, the Index register is at 3B4h
(MDA mode) or 3D3h (CGA mode) and the data port is accessed at 3B5h (MDA mode) or 3D5h (CGA
mode).
Notes:
1. Register CR80 enables / disables the CRTC Extensions, except for register CR41.
2. Group 0 Protection: In the original IBM VGA, CR[0:7] could be write-protected by CR11[7]. In
2. Group 0 Protection: In the original IBM VGA, CR[0:7] could be write-protected by CR11[7]. In
BIOS code, this write protection is set following each mode change. Other protection groups have
no current use, and would not be used going forward by the BIOS or by drivers. They are the result
of an industry trend some years ago to attempt to write protect other groups of registers; however,
all such schemes were chip specific. Only the IBM compatible write protection method (Group 0
Protection) is currently supported.
no current use, and would not be used going forward by the BIOS or by drivers. They are the result
of an industry trend some years ago to attempt to write protect other groups of registers; however,
all such schemes were chip specific. Only the IBM compatible write protection method (Group 0
Protection) is currently supported.
The following figure shows display fields and dimensions and the particular CRxx register that provides
the control.
the control.