Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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9.6.17. CR0F
Text Cursor Location Low Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=0Fh)
Default: Undefined
Default: Undefined
Attributes: Read/Write
This cursor is the text cursor that is part of the VGA standard, and should not be confused with the
hardware cursor and popup (a.k.a., cursor and cursor 2), which are intended to be used in graphics
modes. This text cursor exists only in text modes, and so this register is entirely ignored in graphics modes.
hardware cursor and popup (a.k.a., cursor and cursor 2), which are intended to be used in graphics
modes. This text cursor exists only in text modes, and so this register is entirely ignored in graphics modes.
Bit Description
7:0
Text Cursor Location Bits [7:0]. This field provides the 8 least significant bits of a 16-bit value that
specifies the address offset from the beginning of the frame buffer at which the text cursor is located.
Bits 7:0 of the Text Cursor Location High Register (CR0D) provide the 8 most significant bits.
specifies the address offset from the beginning of the frame buffer at which the text cursor is located.
Bits 7:0 of the Text Cursor Location High Register (CR0D) provide the 8 most significant bits.
9.6.18. CR10
Vertical Sync Start Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=10h)
Default: Undefined
Default: Undefined
Attributes: Read/Write
Bit Description
7:0
Vertical Sync Start Bits [7:0]. This register provides the 8 least significant bits of either a 10-bit or
12-bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active
display area of a screen.
12-bit value that specifies the beginning of the vertical sync pulse relative to the beginning of the active
display area of a screen.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, this value is
described in 10 bits with bits [7,2] of the Overflow Register (CR07) supplying the 2 most significant bits.
described in 10 bits with bits [7,2] of the Overflow Register (CR07) supplying the 2 most significant bits.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, this value is described in
12 bits with bits [3:0] of the Extended Vertical Sync Start Register (CR32) supplying the 4 most
significant bits.
12 bits with bits [3:0] of the Extended Vertical Sync Start Register (CR32) supplying the 4 most
significant bits.
This 10-bit or 12-bit value should equal the vertical sync start in terms of the number of scan lines from
the beginning of the active display area to the beginning of the vertical sync pulse. Since the active
display area always starts on the 0th scan line, this number should be equal to the number of the scan
line on which the vertical sync pulse begins.
the beginning of the active display area to the beginning of the vertical sync pulse. Since the active
display area always starts on the 0th scan line, this number should be equal to the number of the scan
line on which the vertical sync pulse begins.