Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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9.6.23. CR15
Vertical Blanking Start Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=15h)
Default: Undefined
Attributes: Read/Write
Default: Undefined
Attributes: Read/Write
Bit Description
7:0
Vertical Blanking Start Bits [7:0]. This register provides the 8 least significant bits of either a 10-bit or
12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the
active display area of the screen. Whether this value is described in 10 or 12 bits depends on the setting
of bit 0 of the I/O Control Register (CR80).
12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the
active display area of the screen. Whether this value is described in 10 or 12 bits depends on the setting
of bit 0 of the I/O Control Register (CR80).
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical blanking
start is specified with a 10-bit value. The most and second-most significant bits of this value are
supplied by bit 5 of the Maximum Scan Line Register (CR09) and bit 3 of the Overflow Register (CR07),
respectively.
start is specified with a 10-bit value. The most and second-most significant bits of this value are
supplied by bit 5 of the Maximum Scan Line Register (CR09) and bit 3 of the Overflow Register (CR07),
respectively.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical blanking start
is specified with a 12-bit value. The 4 most significant bits of this value are supplied by bits [3:0] of the
Extended Vertical Blanking Start Register (CR33).
is specified with a 12-bit value. The 4 most significant bits of this value are supplied by bits [3:0] of the
Extended Vertical Blanking Start Register (CR33).
This 10-bit or 12-bit value should be programmed to be equal the number of scan lines from the
beginning of the active display area to the beginning of the vertical blanking period. Since the active
display area always starts on the 0th scan line, this number should be equal to the number of the scan
line on which vertical blanking begins.
beginning of the active display area to the beginning of the vertical blanking period. Since the active
display area always starts on the 0th scan line, this number should be equal to the number of the scan
line on which vertical blanking begins.
9.6.24. CR16
Vertical Blanking End Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=16h)
Default: Undefined
Default: Undefined
Attributes: Read/Write
This register provides an 8-bit value that specifies the end of the vertical blanking period relative to its
beginning.
beginning.
Bit Description
7:0
Vertical Blanking End Bits [7:0]. This 8-bit value should be set equal to the least significant 8 bits of
the result of adding the length of the vertical blanking period in terms of the number of scan lines that
occur within the length of the vertical blanking period to the value that specifies the beginning of the
vertical blanking period (see the description of the Vertical Blanking Start Register for details).
the result of adding the length of the vertical blanking period in terms of the number of scan lines that
occur within the length of the vertical blanking period to the value that specifies the beginning of the
vertical blanking period (see the description of the Vertical Blanking Start Register for details).