Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
131
9.6.26. CR18
Line Compare Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=18h)
Default: Undefined
Default: Undefined
Attributes: Read/Write
Bit Description
7:0
Line Compare Bits [7:0]. This register provides the 8 least significant bits of a 10-bit value that
specifies the scan line at which the memory address counter restarts at the value of 0. Bit 6 of the
Maximum Scan Line Register (CR09) supplies the most significant bit, and bit 4 of the Overflow Register
(CR07) supplies the second most significant bit.
specifies the scan line at which the memory address counter restarts at the value of 0. Bit 6 of the
Maximum Scan Line Register (CR09) supplies the most significant bit, and bit 4 of the Overflow Register
(CR07) supplies the second most significant bit.
Normally, this 10-bit value is set to specify a scan line after the last scan line of the active display area.
When this 10-bit value is set to specify a scan line within the active display area, it causes that scan line
and all subsequent scan lines in the active display area to display video data starting at the very first
byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with
the image in the top part being repeated in the bottom part. (This register is only used in split screening
modes, and this is not a problem because split screening is not actually used for extended modes. As a
result, there is no benefit to extending the existing overflow bits for higher resolutions. )
When this 10-bit value is set to specify a scan line within the active display area, it causes that scan line
and all subsequent scan lines in the active display area to display video data starting at the very first
byte of the frame buffer. The result is what appears to be a screen split into a top and bottom part, with
the image in the top part being repeated in the bottom part. (This register is only used in split screening
modes, and this is not a problem because split screening is not actually used for extended modes. As a
result, there is no benefit to extending the existing overflow bits for higher resolutions. )
When used in cooperation with the Start Address High Register (CR0C) and the Start Address Low
Register (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom
parts displaying different data. The top part will display whatever data exists in the frame buffer starting
at the address specified in the two aforementioned start address registers, while the bottom part will
display whatever data exists in the frame buffer starting at the first byte of the frame buffer.
Register (CR0D), it is possible to create a split display, as described earlier, but with the top and bottom
parts displaying different data. The top part will display whatever data exists in the frame buffer starting
at the address specified in the two aforementioned start address registers, while the bottom part will
display whatever data exists in the frame buffer starting at the first byte of the frame buffer.
9.6.27. CR22
Memory Read Latch Data Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=22h)
Default: 00h
Attributes: Read
Default: 00h
Attributes: Read
Only
Bit Description
7:0
Memory Read Latch Data. This field provides the value currently stored in 1 of the 4 memory read
latches. Bits 1 and 0 of the Read Map Select Register (GR04) select which of the 4 memory read
latches may be read via this register.
latches. Bits 1 and 0 of the Read Map Select Register (GR04) select which of the 4 memory read
latches may be read via this register.