Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
135
9.6.32. CR33
Extended Vertical Blanking Start Register
I/O (and Memory Offset) Address: 3B5h/3D5h (index=33h)
Default: 00h
Attributes: Read/Write
Default: 00h
Attributes: Read/Write
7
4
3
0
Reserved (0000)
Vertical Blanking Start Bits 11:8
Bit Description
7:4
Reserved. Read as 0s. This field must be 0s when this register is written.
3:0
Vertical Blanking Start Bits [11:8]. The vertical blanking start is a 10-bit or 12-bit value that specifies
the beginning of the vertical blanking period relative to the beginning of the active display area.
the beginning of the vertical blanking period relative to the beginning of the active display area.
In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical blanking
start is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of
the Vertical Blanking Start Register (CR15), and the most and second-most significant bits are supplied
by bit 5 of the Maximum Scan Line Register (CR09) and bit 3 of the Overflow Register (CR07),
respectively. In standard VGA modes, these four bits are not used.
start is specified with a 10-bit value. The 8 least significant bits of this value are supplied by bits [7:0] of
the Vertical Blanking Start Register (CR15), and the most and second-most significant bits are supplied
by bit 5 of the Maximum Scan Line Register (CR09) and bit 3 of the Overflow Register (CR07),
respectively. In standard VGA modes, these four bits are not used.
In extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, the vertical blanking start
is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits {7:0] of the
Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by these 4 bits of
this register.
is specified with a 12-bit value. The 8 least significant bits of this value are supplied by bits {7:0] of the
Vertical Blanking Start Register (CR15), and the 4 most significant bits are supplied by these 4 bits of
this register.
This 10-bit or 12-bit value should be programmed to be equal to the number of scan line from the
beginning of the active display area to the beginning of the blanking period. Since the active display
area always starts on the 0th scan line, this number should be equal to the number of the scan line on
which the vertical blanking period begins.
beginning of the active display area to the beginning of the blanking period. Since the active display
area always starts on the 0th scan line, this number should be equal to the number of the scan line on
which the vertical blanking period begins.