Intel 815 Manuel D’Utilisation

  

159 

This instruction is used to specify the base address and pitch of the Z buffer surface used by the 3D 
Rendering engine. This is an "immediate" command and therefore software must guarantee that the 
Rendering Engine and the local cache are flushed prior to modifying the z buffer information. The format 
of the GFXCMDPARSER _Z_BUFFER_INFO instruction is: 

  

0 31:29 

Client: 000 – Rendering Processor 

 28:23 

Opcode: 16h 

 22:6 

Reserved. MBZ 

 5:0 

Dword Length: 00h 

1 31:26 

Reserved. 

 25:12 

Base Address: The base address of the Z buffer in linear space. The Memory 
Interface unit uses this address in conjunction with the Memory Fence Table Registers 
to determine the virtual (Tiled) address of the buffer . This surface address (linear) 
must be at least 4KB aligned. in addition it must be 4 times pitch aligned. 

 11:2 

Reserved. 

 1:0 

Pitch: This is the pitch of the Z Buffer. This is used by the TLB in computing the 
absolute address of Z requests.  

00 = 512 bytes 

01 = 1 KB 

10 = 2 KB 

11 = 4 KB 

These instruction causes the active ring buffer Head Pointer to be written to a cacheable (snooped) 
system memory location. The location written is relative to the address programmed in the Hardware 
Status Page Address Register, and depends on which ring buffer is active. (Refer to the description of the 
HSW_PGA register). The format is:  

  

0 31:29 

Client: 000 – Instruction Parser 

 28:23 

Opcode: 07h 

 22:0 

Reserved. MBZ