Intel 815 Manuel D’Utilisation

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0

2.3.1.3.

Software Start-Up Sequence

The following sequence of events will occur during the initialization of an Intel

815 chipset-based

system:

1. The ICH asserts PCIRST# either in response to an initial assertion of PWROK or a write to an I/O

Port.

2. System BIOS runs basic POST code to test the processor.
3. System BIOS initializes the minimum set of Intel

815 chipset configuration registers required to

initiate a PCI configuration cycle towards the AGP/PCI interface (e.g., bus #1). Note that
following a system reset condition, the Intel

815 chipset will always be in “AGP Mode” (Internal

Graphics disabled).

4. System BIOS detects if an AGP graphics card is present by attempting a configuration read cycle

to the Intel

815 chipset AGP/PCI interface. If the configuration cycle completes successfully, then

it is assumed that an external graphics device is present on the AGP interface, and the Intel

815

chipset remains in “AGP Mode” (APCONT[0] = 0). If the AGP/PCI configuration cycle results in
a Master Abort, then it is assumed no external AGP graphics device is present, and the System
BIOS programs the Intel

815 chipset to “Internal Graphics Mode” by setting APCONT[0] = 1.

During the same configuration cycle as setting the APCONT[0] to either 0 or 1, the BIOS should
set APCONT[2] (GFX AGP Select Lock) = 1 to lock the configuration mode.

5. System BIOS will then initialize the minimum set of the Intel

815 chipset configuration registers

required to detect and test system memory.

6. System BIOS interrogates each System Memory DIMM via the Serial Presence Detect (SPD)

mechanism (ICH I2C cycles).

7. System BIOS determines if system configuration is capable of 133 MHz operation. Requirements

for 133 MHz operation include: the Intel

815 chipset in AGP Mode, and System Memory

populated with up to two double-sided, or three single-sided, PC133-compliant DIMMs.

8. If system is 133 MHz capable (as determined by the previous step), System BIOS “upshifts” the

System Memory operating frequency from 100 MHz to 133 MHz as follows (Note that the Intel

815 chipset typically resets internally to 100 MHz SM operation):

a) Program external clock generator chip (i.e., “CK815”) for 133 MHz System Memory

clocking via ICH I2C port (Byte 3, Bit 0 set to 1).

b) Wait for 1 µs to allow the Clock Generator to stabilize the external System Memory clocks

(i.e., SCLK). Note that the Clock Generator must guarantee a “clean” Host Clock (HCLK)
during this entire transition!

c) Program

Intel

815 chipset System Memory Frequency Select bit (GMCHCFG[2]) to 1 to

enable internal System Memory clocking to operate at 133 MHz.

d) Wait at least 0.5 µs for the Intel

815 chipset to re-synchronize internal clocks before

accessing anything other than Intel

815 chipset Configuration registers or the Hub

interface/ICH interface.

9. System BIOS then detects and configures all of system memory, and tests enough memory to

support a stack and an interrupt area.

10. System BIOS should shadow itself and complete system initialization.
11. If and only if the Intel

815 chipset is in Internal Graphics Mode (APCONT[0] = 1), pass control

to the system BIOS internal graphics mode initialization routines described below.

12. System BIOS programs the Intel

815 chipset base addresses using PCI configuration cycles as

described in the PCI Local Bus Specification.

13. PCI enumeration takes place at this point.