Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
262
14.6.
DCLK_0DS—Display & LCD Clock Divisor Select
Register
Address Offset:
06010h–06013h
Default Value:
40404040h
Attributes: R/W
Size: 32
Size: 32
bits
Display clock i {i=0 to 2} becomes effective after programming the appropriate byte i {i = 0 to 2}in this
register. LCD clock becomes effective after programming byte 3 in this register.
register. LCD clock becomes effective after programming byte 3 in this register.
31 30
28 27
26 25
24
Reserved
Post Divisor Select LCD Clk
Reserved
VCO Loop
Div LCD
clk
Reserved
23 22
20 19
18 17
16
Reserved
Post Divisor Select Clk 2
Reserved
VCO Loop
Div clk 2
Reserved
15 14
12 11
10 9
8
Reserved
Post Divisor Select Clk 1
Reserved
VCO Loop
Div clk 1
Reserved
7 6
4
3 2
1
0
Reserved
Post Divisor Select Clk 0
Reserved
VCO Loop
Div clk 0
Reserved
DPLL
DSYNCON
Bit Description
31
Reserved.
30:28
Post Divisor Select LCD Clock.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16 (default)
101 = Divide by 32
11x = Reserved
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16 (default)
101 = Divide by 32
11x = Reserved
27
Reserved.
26
VCO Loop Divide LCD Clock.
0 = Divided by 4 (default)
1 = Divided by 16
1 = Divided by 16
25:23
Reserved.