Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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15.4.11. OV0CMD—Overlay Command Register
Memory Address Offset:
68h (R/W)
On-chip Reg. Mem Addr Offset:
30168h (RO; debug path)
Default Value:
00h
Access:
see address offset above
Size:
32 bits
This register provides the data the overlay engine needs to begin work. A write to this register sets an
internal bit (readable by the status) that will cause all the register values that were written to be internally
latched and become active on the next VBLANK event.
internal bit (readable by the status) that will cause all the register values that were written to be internally
latched and become active on the next VBLANK event.
31
30
28
27
25
24
Sel. Top
OV
(Rsvd)
Vertical Chrom Filter
Vertical Luminance Filter
Horiz
Chrom
Filter
[24:22]
23 22
21
19
18 17
16
Horiz. Chrom Filter
(cont)
Horizontal Luminance Filter
Mirroring
Y Adj
15
14 13
10
9
8
4:2:2: Byte Order
Source Format
Flip TV-
Out Field
Sel.
Flip Qual
[8:7]
7 6 5 4 3
2
1
0
Flip Qual
(Cont)
Vert. Initial
Phase Sel.
Disp Flip
Type
Ignore Buf
and Field
Reserved
Buffer and Field
Overlay
Enable