Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
301
16. Instruction, Memory, and Interrupt
Control Registers
16.1.
Instruction Control Registers
16.1.1. FENCE—Graphics Memory Fence Table Registers
Address Offset:
02000h – 0201Fh
Default Value:
00000000h
Access:
Read/32 bit Write only
Size:
8x 32 bits each
The Memory Hub (MH) performs address translation between linear space and tiled space. The intent of
tiling is to locate graphics data that are close (in X and Y surface axes) in one memory page while still
locating some amount of line oriented data sequentially in memory for display efficiency. All 3D
rendering is done such that the QWords of any one span are all located in the same memory page, which
improves rendering performance.
tiling is to locate graphics data that are close (in X and Y surface axes) in one memory page while still
locating some amount of line oriented data sequentially in memory for display efficiency. All 3D
rendering is done such that the QWords of any one span are all located in the same memory page, which
improves rendering performance.
Tiled memory is supported for rendering surfaces located in graphics memory. A tiled memory surface is
a surface, which has a secondary pitch and height, which are subsets of the surface’s total pitch and
height. The graphics controller maintains the constants required by the memory interface to perform the
address translations for up to eight tiled regions (each with a different pitch and size).
a surface, which has a secondary pitch and height, which are subsets of the surface’s total pitch and
height. The graphics controller maintains the constants required by the memory interface to perform the
address translations for up to eight tiled regions (each with a different pitch and size).
The memory interface needs the surface pitch and tile height to perform the address translation. It uses
the fence base address, size constants and the surface address to determine if the rendering surface is
tiled and swizzle the bits as required by tiling. Since fence ranges are at least 512 KB and aligned, 7
address bits are required to specify the lower bound. In addition, the fence lower bound must be fence
size aligned.
the fence base address, size constants and the surface address to determine if the rendering surface is
tiled and swizzle the bits as required by tiling. Since fence ranges are at least 512 KB and aligned, 7
address bits are required to specify the lower bound. In addition, the fence lower bound must be fence
size aligned.
A Tile represents 2 KB of memory. Tile height is fixed at 16. Based on this the surface pitch has to be
programmed in tiles. Eight Fence Table Registers occupy the address range specified above. Each Fence
Table Register has the following format.
programmed in tiles. Eight Fence Table Registers occupy the address range specified above. Each Fence
Table Register has the following format.
Note that X and Y major tiles are used for Host, texture, and Blitter source and destination surfaces.
Display, Overlay, motion comp source, dest surfaces, color and Z surfaces if tiled must be X major.
Display, Overlay, motion comp source, dest surfaces, color and Z surfaces if tiled must be X major.
31 26
25
19
18 16
Reserved
Fence Lower Bound
Reserved
15 14
13 12
11 10
8
Reserved Reserved Tile
Walk
Reserved
Fence
Size
7
6
4
3
1
0
Reserved Fence
Pitch
Reserved
Fence
Valid