Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
304
16.1.3. PGTBL_ER—Page Table Error Register
Address Offset:
02024h (identical functionality in Device 0 at EC–EFh)
Default Value:
0000 0000h
Access: Read
Only
Size: 32
bits
This register stores information pertaining to page table error interrupts. Invalid physical address implies
regions in main memory that have restricted accessibility such as PAM/SMM space etc.
regions in main memory that have restricted accessibility such as PAM/SMM space etc.
The Display engine speculatively fetches data, and may cross 16 GTT mapped pages that are not
intended for use. To prevent errors from occurring and hanging the display engine, the 16 GTT pages
adjacent to the contiguous display region must be left unused but marked valid and mapped.
intended for use. To prevent errors from occurring and hanging the display engine, the 16 GTT pages
adjacent to the contiguous display region must be left unused but marked valid and mapped.
Once a page table error has been detected, the GMCH hardware will operate in an error state but
continues to complete host cycles to memory in order to facilitate system debug (as opposed to hanging
the system.) In the page table error detected state, further read will complete normally, whereas write will
complete with all byte enables masked.
continues to complete host cycles to memory in order to facilitate system debug (as opposed to hanging
the system.) In the page table error detected state, further read will complete normally, whereas write will
complete with all byte enables masked.
The page table error condition within the GMCH can be recovered by software writing a ‘1’ to bit 15 of
the Interrupt Identity Register (IIR.) Note that this action is in addition to software clearing the page table
error identification bit in the Error Identity Register (EIR[4].)
the Interrupt Identity Register (IIR.) Note that this action is in addition to software clearing the page table
error identification bit in the Error Identity Register (EIR[4].)
31
12
11
6
5 3
2 0
Physical Address 31:12
Reserved
Error ID
Error Type
Bit Description
31:12
Physical Address. This field provides the page table access address for a page table Error Type 4,
(i.e. bits 2:0 = “100”) indicating a translated address that points to PAM, SMM, and other restricted
spaces in main memory. This field is normally undefined and only registers a valid entry upon an
occurrence of a page table error type 4. Occurrence of a page table error type 4 is recorded in
MMIO register 20B8h, Error Status Register, bit 4.
(i.e. bits 2:0 = “100”) indicating a translated address that points to PAM, SMM, and other restricted
spaces in main memory. This field is normally undefined and only registers a valid entry upon an
occurrence of a page table error type 4. Occurrence of a page table error type 4 is recorded in
MMIO register 20B8h, Error Status Register, bit 4.
11:6
Reserved
5:3
Error Identification: Identifies the TLB that caused the error. After an error Render, Mapping and
Blitter engines will stop execution. However, overlay, display and host operations will not stop. Each
Source records the first error and ignores subsequent errors. See the Page Table Error Mask
Register for more debug help.
Blitter engines will stop execution. However, overlay, display and host operations will not stop. Each
Source records the first error and ignores subsequent errors. See the Page Table Error Mask
Register for more debug help.
000 = Buffer (BF) Unit
001 = Overlay
010 = Display
011 = Host
100 = Render
101 = Blitter
110 = Mapping
111 = Command Stream
001 = Overlay
010 = Display
011 = Host
100 = Render
101 = Blitter
110 = Mapping
111 = Command Stream