Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
320
16.2.
Interrupt Control Registers
The interrupt control registers described below all share the same bit definition. The bit definition is as
follows:
follows:
15 14
13 12
11
10
9
8
HW
Detect
Error
Master
Reserved Sync
Status
Toggle
Pri Dply
Flip
Pending
Reserved Overlay
0
Flip
Pending
Rsvd
7 6 5 4 3 2 1 0
Pri Dply
VBLANK.
Pri Dply
Event
Reserved
Reserved
Reserved
Reserved
User
Defined
Interrupt
Breakpoint
Table 17.
Bit Definition For Interrupt Control Registers
Bit Description
15
Hardware Detected Error Master. When this status bit is set, it indicates that the hardware has
detected an error. Set on an error condition and cleared by a processor write of a one to the
appropriate bit contained in the error id register followed by a write of a one to this bit in the IIR.
Further information on the source of the error comes from the “Error Status Register” which along with
the “Error Mask Register” determine which error conditions will cause the error status bit and the
interrupt to occur. The intent is to use the error bits to detect errors during debug and testing. Error
conditions during normal operation should not occur.
detected an error. Set on an error condition and cleared by a processor write of a one to the
appropriate bit contained in the error id register followed by a write of a one to this bit in the IIR.
Further information on the source of the error comes from the “Error Status Register” which along with
the “Error Mask Register” determine which error conditions will cause the error status bit and the
interrupt to occur. The intent is to use the error bits to detect errors during debug and testing. Error
conditions during normal operation should not occur.
• MM/LM Refresh timer error: Indicates a refresh request buffer overrun.
• Page Table Error: Indicates a page table error.
• Display or Overlay under run: Set on either a display or overlay under run error. See display and
overlay status registers to determine source of the error.
• Instruction Parser Error: The Instruction Parser encounters an error while parsing an instruction.
14:13
Reserved
12
Sync Status Toggle. This bit is toggled when the instruction parser completes a flush with the sync
enable bit active in the instruction parser mode register. The toggle event will happen after all the
graphics engines are flushed. The store dword resulting from this toggle will cause the processor’s
view of graphics memory to be coherent as well (invalidate the host graphics cache).
enable bit active in the instruction parser mode register. The toggle event will happen after all the
graphics engines are flushed. The store dword resulting from this toggle will cause the processor’s
view of graphics memory to be coherent as well (invalidate the host graphics cache).
11
Primary Display Flip Pending. Status bit is set on a pending flip and cleared when the flip occurs,
whereas IIR reflects Flip-Occurred# (which is contrary to the general definition of setting of IIR bits
when interrupts occur). This is only used when the GFXCMDPARSER_FRONT_BUFFER _INFO
packet is being used. See that instruction for additional information. To prevent race conditions, the
status write occur before the STOREDWORD following the flip packet is written.
whereas IIR reflects Flip-Occurred# (which is contrary to the general definition of setting of IIR bits
when interrupts occur). This is only used when the GFXCMDPARSER_FRONT_BUFFER _INFO
packet is being used. See that instruction for additional information. To prevent race conditions, the
status write occur before the STOREDWORD following the flip packet is written.
10
Reserved