Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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16.3.
Display Interface Control
16.3.1. FW_BLC—FIFO Watermark and Burst Length Control
Address Offset :
020D8h
Default Value:
22 31 73 17h
Access: Read/Write
Size: 32
Size: 32
bits
These control values only apply to HIRes modes of operation. VGA modes ignore the settings of these
registers in favor of fixed values.
registers in favor of fixed values.
For VGA Text mode, character buffer fetches are performed without regard to the space available in the
FIFO (since this data is stored in the character buffer, not the FIFO). Character buffer fetches are
performed as a single request of 8 QWs. Font data is fetched one QW at a time, and will begin when the
FIFO has room for 8 character font QWs. VGA Graphics modes will perform requests one at a time so
long as there is room for 1 QW in the FIFO.
FIFO (since this data is stored in the character buffer, not the FIFO). Character buffer fetches are
performed as a single request of 8 QWs. Font data is fetched one QW at a time, and will begin when the
FIFO has room for 8 character font QWs. VGA Graphics modes will perform requests one at a time so
long as there is room for 1 QW in the FIFO.
1. FIFOs refer to ALL FIFOs in the DSI data path (i.e. The total FIFO space available is the sum of
the DSI FIFO depth and the Display Engine FIFO depth). Currently, this depth is 48 QWs.
2. The h/w default is an invalid value: these quantities should never be programmed to zeros.
3. The hardware depends on these registers being set properly since it is possible to set the request
3. The hardware depends on these registers being set properly since it is possible to set the request
length and watermarks to states which would cause the overflow of the sync FIFO. For example,
assume a watermark is set to 33 QW and the request length is set to 32 QWs. When the first two
requests have been completed, 64 QWs will have been written into the sync FIFO. During this
time, only 16 QWs will be drained out of the FIFO to be written to the Display Engine FIFO. Since
the sync FIFO in the DSI is only 32 QWs deep, this will result in (64-16-32) = 16 QW overflow of
the FIFO.
assume a watermark is set to 33 QW and the request length is set to 32 QWs. When the first two
requests have been completed, 64 QWs will have been written into the sync FIFO. During this
time, only 16 QWs will be drained out of the FIFO to be written to the Display Engine FIFO. Since
the sync FIFO in the DSI is only 32 QWs deep, this will result in (64-16-32) = 16 QW overflow of
the FIFO.
31
28
27
24
Overlay Delay Timer1
Overlay Delay Timer0
23 22
20
19 18
17
12 11 10
8
Rsvd MM
Dply
Burst
Length
Reserved
MM Display FIFO
Watermark
Rsvd LM
Display
Burst
Length
7 6
5
0
Overlay Watermark
Reserved