Intel 815 Manuel D’Utilisation

  

49 

The graphics adapter state should be restored by performing the following steps. Note some of the 
synchronization operations, especially those that ensure that the local memory is idle during the state 
restore. Also, much of the work involves reprogramming the registers with the values captured during the 
save-state operation. 

•  Blank the screen. 
•  Turn off DRAM refresh. 

  Read the value of the DRAM_CONTROL_HI Register (MM 0x3002). 

  Set the DRAM Refresh Rate bits (DDR Bits 4:3) to Disable_Refresh (value 0). 

  Write the modified value back to the DRAM_CONTROL_HI Register. 

•  Write the M, N, and P (i.e., the Divisor Select value) values from the saved state information. 
•  Restore the 8-bit DAC mode to what it was when the state was saved, but preserve the current value 

of the rest of the register containing this flag: 

  Read the Pixel Pipeline Configuration 0 Register. 

  Clear the current value of the 8- or 6-bit DAC mode. 

  OR–in (only) the value of the DAC_8_BIT from saved register information of the Pixel 

Pipeline Configuration 0 Register. 

  Write the result back to the Pixel Pipeline Configuration 0 Register. 

•  Restore the generic VGA registers to the values captured at save-state time. 
•  Restore the following registers to their saved state values: 

  Vertical Total 

CRX 30 

  Vertical Display End 

CRX 31 

  Vertical Sync Start 

CRX 32 

  Vertical Blank Start 

CRX 33 

  Horizontal Total 

CRX 35 

  Horizontal Blnk 

CRX 39 

  Ext Offset 

CRX 41 

•  The following registers should restore only certain bits from the saved state values: 

Interlace Control 

CRX 70 

  Read the current value. 

  Clear the interlace enable bit. 

  OR–in the saved value of the Interlace Control Register. 

  Write the result back into the Interlace Control Register. 

Address Mapping: 

GR10 

  Read the current value of the Address Mapping Register. 

  Save only the reserved bits values (bits 7:5). 

  OR–in the saved value of the Address Mapping Register. 

  Write the result back into the Address Mapping Register. 

•  Now the DRAM refresh can be turned on: 

  Read the value of the DRAM_CONTROL_HI Register. 

  Turn off the DRAM_REFRESH_RATE bits. 

  OR–in a 60-Hz refresh rate value. 

  Write the result back into the DRAM_CONTROL_HI Register.