Intel 815 Manuel D’Utilisation
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
83
9.1.4. MSR
Miscellaneous Output
I/O (and Memory Offset) Address: 3C2h
Write;
3CCh
Read
Default: 00h
Attributes:
Attributes:
See Address above
7 6 5 4
3
2
1 0
VSYNC
Polarity
HSYNC
Polarity
Page
Select
Reserved
(0)
Clock Select
A0000
−
BFFFFh
Acc En
I/O
Address
Bit Descriptions
7
CRT VSync Polarity.
0 = Positive Polarity (default).
1 = Negative Polarity.
1 = Negative Polarity.
6
CRT HSync Polarity.
0 = Positive Polarity (default).
1 = Negative Polarity
1 = Negative Polarity
5
Page Select. In Odd/Even Memory Map Mode 1 (GR6), this bit selects the upper or lower 64 KB page in
display memory for processor access:
display memory for processor access:
0 = Upper page (default)
1 = Lower page.
1 = Lower page.
Selects between two 64 KB pages of frame buffer memory during standard VGA odd/even modes
(modes 0h through 5h). Bit 1 of register GR06 can also program this bit in other modes. Note that this bit
is always set to 1 by the driver software.
(modes 0h through 5h). Bit 1 of register GR06 can also program this bit in other modes. Note that this bit
is always set to 1 by the driver software.
4
Reserved. Read as 0.
3:2
Clock Select. These bits usually select the dot clock source for the CRT interface. The bits select the dot
clock in standard VGA modes.
clock in standard VGA modes.
00 = CLK0, 25 MHz (for standard VGA modes with 640 pixel horizontal resolution) (default)
01 = CLK1, 28 MHz. (for standard VGA modes with 720 pixel horizontal resolution)
1x = CLK2 (left “reserved” in standard VGA, used for all extended modes 6 MHz–135 MHz)
01 = CLK1, 28 MHz. (for standard VGA modes with 720 pixel horizontal resolution)
1x = CLK2 (left “reserved” in standard VGA, used for all extended modes 6 MHz–135 MHz)
1
A0000
−−−−BFFFFh Access Enable. VGA Compatibility bit enables access to local video memory (frame
buffer) at A0000
−BFFFFh. When disabled, accesses to system memory are blocked in this region (by not
asserting DEVSEL#). This bit does not block processor access to the video linear frame buffer at other
addresses.
addresses.
0 = Prevent processor access to frame buffer (default).
1 = Allow processor access to frame buffer.
1 = Allow processor access to frame buffer.
0
I/O Address Select. This bit selects 3Bxh or 3Dxh as the I/O address for the CRT Controller registers,
the Feature Control Register (FCR), and Input Status Register 1 (ST01). Presently ignored (whole range
is claimed), but will “ignore” 3Bx for color configuration or 3Dx for monochrome.
the Feature Control Register (FCR), and Input Status Register 1 (ST01). Presently ignored (whole range
is claimed), but will “ignore” 3Bx for color configuration or 3Dx for monochrome.
0 = Select 3Bxh I/O address (MDA emulation) (default).
1 = Select 3Dxh I/O address (CGA emulation).
1 = Select 3Dxh I/O address (CGA emulation).
NOTES:
1. In standard VGA modes, bits 7 and 6 indicate which of the three standard VGA vertical resolutions the
standard VGA display should use. All extended modes, including those with a vertical resolution of 480 scan
lines, use a setting of 0 for both of these bits. This setting was “reserved” in the VGA standard.
lines, use a setting of 0 for both of these bits. This setting was “reserved” in the VGA standard.