Intel 253666-024US Manuel D’Utilisation
3-62 Vol. 2A
ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-M
ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision
Floating-Point Values
Description
Inverts the bits of the four packed single-precision floating-point values in the desti-
nation operand (first operand), performs a bitwise logical AND of the four packed
single-precision floating-point values in the source operand (second operand) and
the temporary inverted result, and stores the result in the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
nation operand (first operand), performs a bitwise logical AND of the four packed
single-precision floating-point values in the source operand (second operand) and
the temporary inverted result, and stores the result in the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[127:0] ← (NOT(DEST[127:0])) BitwiseAND (SRC[127:0]);
Intel C/C++ Compiler Intrinsic Equivalent
ANDNPS __m128 _mm_andnot_ps(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#NM
If CR0.TS[bit 3] = 1.
#UD
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
If the LOCK prefix is used.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
If the LOCK prefix is used.
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F 55 /r
ANDNPS xmm1, xmm2/m128 Valid
Valid
Bitwise logical AND NOT of
xmm2/m128 and xmm1.