Intel 253666-024US Manuel D’Utilisation
Vol. 2A 3-75
INSTRUCTION SET REFERENCE, A-M
BT—Bit Test
BT—Bit Test
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at
the bit-position designated by the bit offset (specified by the second operand) and
stores the value of the bit in the CF flag. The bit base operand can be a register or a
memory location; the bit offset operand can be a register or an immediate value:
the bit-position designated by the bit offset (specified by the second operand) and
stores the value of the bit in the CF flag. The bit base operand can be a register or a
memory location; the bit offset operand can be a register or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16,
32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode).
32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode).
•
If the bit base operand specifies a memory location, the operand represents the
address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced by the
offset operand depends on the operand size.
address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced by the
offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-10.
Some assemblers support immediate bit offsets larger than 31 by using the imme-
diate bit offset field in combination with the displacement field of the memory
operand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit
operands) of the immediate bit offset are stored in the immediate bit offset field, and
the high-order bits are shifted and combined with the byte displacement in the
addressing mode by the assembler. The processor will ignore the high order bits if
they are not zero.
When accessing a bit in memory, the processor may access 4 bytes starting from the
memory address for a 32-bit operand size, using by the following relationship:
Some assemblers support immediate bit offsets larger than 31 by using the imme-
diate bit offset field in combination with the displacement field of the memory
operand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit
operands) of the immediate bit offset are stored in the immediate bit offset field, and
the high-order bits are shifted and combined with the byte displacement in the
addressing mode by the assembler. The processor will ignore the high order bits if
they are not zero.
When accessing a bit in memory, the processor may access 4 bytes starting from the
memory address for a 32-bit operand size, using by the following relationship:
Effective Address + (4 ∗ (BitOffset DIV 32))
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F A3
BT r/m16, r16
Valid
Valid
Store selected bit in CF
flag.
0F A3
BT r/m32, r32
Valid
Valid
Store selected bit in CF
flag.
REX.W + 0F A3
BT r/m64, r64
Valid
N.E.
Store selected bit in CF
flag.
0F BA /4 ib BT
r/m16, imm8 Valid
Valid
Store selected bit in CF
flag.
0F BA /4 ib
BT r/m32, imm8 Valid
Valid
Store selected bit in CF
flag.
REX.W + 0F BA /4 ib
BT r/m64, imm8 Valid
N.E.
Store selected bit in CF
flag.