Intel 253666-024US Manuel D’Utilisation
3-84 Vol. 2A
BTS—Bit Test and Set
INSTRUCTION SET REFERENCE, A-M
BTS—Bit Test and Set
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at
the bit-position designated by the bit offset operand (second operand), stores the
value of the bit in the CF flag, and sets the selected bit in the bit string to 1. The bit
base operand can be a register or a memory location; the bit offset operand can be a
register or an immediate value:
the bit-position designated by the bit offset operand (second operand), stores the
value of the bit in the CF flag, and sets the selected bit in the bit string to 1. The bit
base operand can be a register or a memory location; the bit offset operand can be a
register or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16,
32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode). This allows any
bit position to be selected.
32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode). This allows any
bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the
address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced by the
offset operand depends on the operand size.
address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced by the
offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-10.
Some assemblers support immediate bit offsets larger than 31 by using the imme-
diate bit offset field in combination with the displacement field of the memory
operand. See “BT—Bit Test” in this chapter for more information on this addressing
mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be
executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix
in the form of REX.R permits access to additional registers (R8-R15). Using a REX
Some assemblers support immediate bit offsets larger than 31 by using the imme-
diate bit offset field in combination with the displacement field of the memory
operand. See “BT—Bit Test” in this chapter for more information on this addressing
mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be
executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix
in the form of REX.R permits access to additional registers (R8-R15). Using a REX
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F AB
BTS r/m16, r16
Valid
Valid
Store selected bit in CF
flag and set.
0F AB
BTS r/m32, r32
Valid
Valid
Store selected bit in CF
flag and set.
REX.W + 0F AB
BTS r/m64, r64
Valid
N.E.
Store selected bit in CF
flag and set.
0F BA /5 ib
BTS r/m16, imm8
Valid
Valid
Store selected bit in CF
flag and set.
0F BA /5 ib
BTS r/m32, imm8
Valid
Valid
Store selected bit in CF
flag and set.
REX.W + 0F BA /5 ib
BTS r/m64, imm8
Valid
N.E.
Store selected bit in CF
flag and set.