Intel 253666-024US Manuel D’Utilisation

Vol. 2A 3-213

INSTRUCTION SET REFERENCE, A-M

CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-

Precision Floating-Point Values

CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to 

Packed Double-Precision Floating-Point Values

Description

Converts two packed single-precision floating-point values in the source operand 
(second operand) to two packed double-precision floating-point values in the desti-
nation operand (first operand). 
The source operand can be an XMM register or a 64-bit memory location. The desti-
nation operand is an XMM register. When the source operand is an XMM register, the 
packed single-precision floating-point values are contained in the low quadword of 
the register. 
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional 
registers (XMM8-XMM15).

Operation

DEST[63:0] ← Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);

DEST[127:64] ← Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent

CVTPS2PD

__m128d _mm_cvtps_pd(__m128 a)

SIMD Floating-Point Exceptions

Invalid, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS, 

ES, FS or GS segments.

#SS(0) 

For an illegal address in the SS segment. 

#PF(fault-code) 

For a page fault.

#NM

If CR0.TS[bit 3] = 1. 

#XM 

If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 1. 

Opcode

Instruction

64-Bit 

Mode

Compat/

Leg Mode

Description

0F  5A /r

CVTPS2PD xmm1, 

Valid

Valid

Convert two packed single-precision 

floating-point values in xmm2/m64 

to two packed double-precision 

floating-point values in xmm1.