Intel 253666-024US Manuel D’Utilisation
Vol. 2A 3-219
INSTRUCTION SET REFERENCE, A-M
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to
Doubleword Integer
Description
Converts a double-precision floating-point value in the source operand (second
operand) to a signed doubleword integer in the destination operand (first operand).
The source operand can be an XMM register or a 64-bit memory location. The desti-
nation operand is a general-purpose register. When the source operand is an XMM
register, the double-precision floating-point value is contained in the low quadword of
the register.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operation. See the summary chart at the beginning of this
section for encoding data and limits.
operand) to a signed doubleword integer in the destination operand (first operand).
The source operand can be an XMM register or a 64-bit memory location. The desti-
nation operand is a general-purpose register. When the source operand is an XMM
register, the double-precision floating-point value is contained in the low quadword of
the register.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operation. See the summary chart at the beginning of this
section for encoding data and limits.
Operation
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] ← Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
ELSE
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
int _mm_cvtsd_si32(__m128d a)
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 2D /r CVTSD2SI
r32,
xmm/m64
Valid
Valid
Convert one double-precision
floating-point value from
xmm/m64 to one signed
doubleword integer r32.
F2 REX.W 0F 2D /r
CVTSD2SI r64,
xmm/m64
Valid
N.E.
Convert one double-precision
floating-point value from
xmm/m64 to one signed
quadword integer sign-
extended into r64.