Intel 253666-024US Manuel D’Utilisation
3-234 Vol. 2A
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
INSTRUCTION SET REFERENCE, A-M
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to
Doubleword Integer
Description
Converts a single-precision floating-point value in the source operand (second
operand) to a signed doubleword integer (or signed quadword integer if operand size
is 64 bits) in the destination operand (first operand). The source operand can be an
XMM register or a memory location. The destination operand is a general-purpose
register. When the source operand is an XMM register, the single-precision floating-
point value is contained in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operands. See the summary chart at the beginning of this
section for encoding data and limits.
operand) to a signed doubleword integer (or signed quadword integer if operand size
is 64 bits) in the destination operand (first operand). The source operand can be an
XMM register or a memory location. The destination operand is a general-purpose
register. When the source operand is an XMM register, the single-precision floating-
point value is contained in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operands. See the summary chart at the beginning of this
section for encoding data and limits.
Operation
IF 64-bit Mode and OperandSize = 64
THEN
DEST[64:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
int _mm_cvtss_si32(__m128d a)
Opcode
Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 2D /r
CVTSS2SI r32,
xmm/m32
Valid
Valid
Convert one single-precision
floating-point value from
xmm/m32 to one signed
doubleword integer in r32.
F3 REX.W 0F 2D /r
CVTSS2SI r64,
xmm/m32
Valid
N.E.
Convert one single-precision
floating-point value from
xmm/m32 to one signed
quadword integer in r64.