Intel 253666-024US Manuel D’Utilisation

3-274 Vol. 2A

DIVSD—Divide Scalar Double-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

DIVSD—Divide Scalar Double-Precision Floating-Point Values

Description

Divides the low double-precision floating-point value in the destination operand (first 
operand) by the low double-precision floating-point value in the source operand 
(second operand), and stores the double-precision floating-point result in the desti-
nation operand. The source operand can be an XMM register or a 64-bit memory 
location. The destination operand is an XMM register. The high quadword of the desti-
nation operand remains unchanged. See Chapter 11 in the Intel® 64 and IA-32 
Architectures Software Developer’s Manual, Volume 1, for an overview of a scalar 
double-precision floating-point operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional 
registers (XMM8-XMM15).

Operation

DEST[63:0]← DEST[63:0] / SRC[63:0];

(* DEST[127:64] unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent

DIVSD

__m128d _mm_div_sd (m128d a, m128d b)

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS, 

ES, FS or GS segments.

#SS(0) 

For an illegal address in the SS segment. 

#PF(fault-code) 

For a page fault.

#NM

If CR0.TS[bit 3] = 1. 

#XM 

If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1. 

#UD 

If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0.

Opcode

Instruction

64-Bit 

Mode

Compat/

Leg Mode

Description

F2 0F 5E /r

DIVSD xmm1, 

Valid

Valid

Divide low double-precision floating-

point value n xmm1 by low double-

precision floating-point value in